Patent US4454433A successfully refreshed from Google Patents.
US4454433A
Expired / Lapsed
US
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Multiplier circuit
Assignee: Shawmut Bank NA
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Filing: 1981-08-17
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Granted: 1984-06-12
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Expires: 2001-08-17
Abstract
Abstract The invention relates to an improved voltage control amplifier of the type comprising a gain cell. The gain cell is of the type that includes at least one log transistor for each polarity of input signal and at least one antilog transistor for each log transistor, means for algebraically summing a control signal with the log signal provided by each log transistor and means for providing a symmetry adjust signal to the base of a selected transistor of the cell so that the cell provides substantially the same gain for each polarity of input signal when the control signal level is set for zero. The improvement comprises means for generating a correction signal as a function of the control signal level so as to substantially correct for differences between the early effects exhibited by said transistors as said control signal varies and means for applying the correction signal to the base of one the transistors.
Inventors
- 👤 David R. Welland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:21
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/24
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
193 words
In a signal multiplier of the type comprising an operational amplifier and a gain cell connected to said amplifier, said gain cell having an input terminal for receiving an input signal and a control signal terminal for receiving a control signal, said gain cell comprising two signal processing paths respectively for the positive and negative portions of said input signal, and means for coupling said control terminal to each of said paths, each of said paths including (a) at least one first transistor for providing a log signal as a logarithmic function of the corresponding portion of the input signal and (b) a corresponding at least one second transistor coupled to said first transistor for providing an antilog signal as an antilogarithmic function of the algebraic sum of said log signal and said control signal, the improvement comprising means coupled to said control terminal for generating a correction signal as a function of said control signal so as to substantially correct for differences between the Early effects exhibited by said transistors of each path as said control signal varies and for applying said correction signal to the base of one of said transistors.
Claim 2
Dependent Claim
193 words
In a signal multiplier of the type comprising an operational amplifier and a gain cell connected to said amplifier, said gain cell having an input terminal for receiving an input signal and a control signal terminal for receiving a control signal, said gain cell comprising two signal processing paths respectively for the positive and negative portions of said input signal, and means for coupling said control terminal to each of said paths, each of said paths including (a) at least one first transistor for providing a log signal as a logarithmic function of the corresponding portion of the input signal and (b) a corresponding at least one second transistor coupled to said first transistor for providing an antilog signal as an antilogarithmic function of the algebraic sum of said log signal and said control signal, the improvement comprising means coupled to said control terminal for generating a correction signal as a function of said control signal so as to substantially correct for differences between the Early effects exhibited by said transistors of each path as said control signal varies and for applying said correction signal to the base of one of said transistors.
Claim 3
Dependent Claim
29 words
A signal multiplier according to claim 1, wherein the amplitude level of said correction signal PG,18 is substantially a linear function of the amplitude level of said control signal.
Claim 4
Dependent Claim
34 words
A signal multiplier according to claim 2, wherein said means for generating said correction signal includes a first resistor coupled between said control input terminal and the base of said one of said transistors.
Claim 5
Dependent Claim
50 words
A signal multiplier according to claim 3, further including a symmetry adjust terminal and means for coupling said symmetry adjust terminal to the base of said one of said transistors, wherein said first resistor is coupled between the base of said one of said transistors, and said control signal terminal.
Claim 6
Dependent Claim
54 words
A signal multiplier according to claim 4, wherein said means for coupling said symmetry adjust terminal includes a second resistor coupled between the base of said one of said transistors and system ground so that said first and second resistors function as a voltage divider for said control signal to generate said correction signal.
Claim 7
Dependent Claim
25 words
A signal multiplier according to claim 5, wherein the ratio of the resistance values of said second resistor to said first resistor is approximately 1:4000.
Claim 8
Dependent Claim
30 words
A signal multiplier according to claim 3, further including a symmetry adjust terminal and means for coupling said symmetry adjust terminal to the base of another one of said transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-06-12 | 1987-12-12 | 1988-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-06-12 | 1991-12-12 | 1992-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-06-12 | 1995-12-12 | 1996-06-12 | $7700.00 | Window Closed / Lapsed |