Sense amplifier for MOS static memory array

Claim 2

A sense amplifier circuit comprising: means for generating a variable reference voltage that tracks a variable power supply voltage by a first predetermined voltage difference from said power supply voltage; differential amplifier means having a first input coupled to a memory cell line and a second input coupled to receive said reference voltage; and voltage clamping circuit means coupled to said memory cell line for restricting negative voltage excursions on said memory cell line to lie within a second predetermined voltage difference below said reference voltage.

Claim 3

The sense amplifier of claim 1 wherein said reference voltage is substantially closer to said power supply voltage than to a ground level.

Claim 4

The sense amplifier circuit of claim 2 further comprising pull-up circuit means for pulling said memory cell line toward said power supply voltage.

Claim 5

The sense amplifier circuit of claim 3 wherein said pull-up circuit means is biased to operate in a linear mode for voltages applied thereto from said memory cell line between said power supply voltage and said reference voltage and to operate in a saturation mode for voltages supplied thereto from said memory cell line below said reference voltage.

Claim 6

The sense amplifier of claim 2 wherein said voltage clamping circuit means comprises means for maintaining said second predetermined voltage difference at a fixed value with respect to said reference voltage.

Claim 7

The sense amplifier circuit of any one of claims 1-5 further comprising output level shifting circuit means for shifting in range a voltage outputted by said differential amplifier means.

Claim 8

The sense amplifier of any one of claims 1-5 wherein said reference voltage generating means comprises depletion mode first and second FETs having channels connected in series between a terminal receiving said power supply voltage and ground with a gate and one of a source and drain of said first FET being connected to said terminal and a gate and the other of said source and drain of said second FET being connected to ground, said reference voltage being produced at a common connection point between said first and second FETs.

Claim 9

The sense amplifier of any one of claims 1-5 wherein said voltage clamping circuit means comprises depletion mode first and second FETs having channels connected in series between a terminal receiving said power supply voltage and ground with a gate and one of a source and drain of said first FET being connected to said terminal and a gate and the other of said source and drain of said second FET being connected to ground, and an enhancement mode third FET having a gate connected to a common connection point between said first and second FETs and said one of said source and drain connected to said terminal, said other one of said source and drain of said third FET being connected to said memory cell line.

Claim 10

A bit line sense amplifier for a semiconductor memory comprising: a depletion mode first FET having a gate and drain connected to a source of a positive supply voltage terminal; a depletion mode second FET having a gate and source connected to ground and a drain connected to a source of said first FET; an enhancement mode third FET having a drain connected to said positive terminal, a gate connected to said source of said first FET and a source connected to a bit line; a depletion mode fourth FET having a drain connected to said positive terminal and a gate a source connected to said bit line; a depletion mode fifth FET having a drain connected to said positive terminal and a gate connected to said bit line; a depletion mode sixth FET having a drain connected to said positive terminal; an enhancement mode seventh FET having a drain connected to a source of said fifth FET and a source connected to ground; an enhancement mode eighth FET having a gate and drain connected to a source of said sixth FET and to a gate of said seventh FET, and a source connected to ground; a depletion mode ninth FET having a drain and gate connected to said positive terminal and a source connected to a gate of said sixth FET; a depletion mode tenth FET havin a drain connected to said source of said ninth FET and a gate and source connected ground; a depletion mode eleventh FET having a drain connected to said positive terminal; and an enhancement mode twelfth FET having a drain connected to a source and gate of said eleventh FET, a gate connected to said drain of said seventh FET, and a source connected to ground, an output signal being produced on said drain of said twelfth FET.

Claim 11

A bit line sense amplifier for a semiconductor memory comprising: a depletion mode first FET having a gate and drain connected to a source of a positive supply voltage terminal; a depletion mode second FET having a gate and source connected to ground and a drain connected to a source of said first FET; an enhancement mode third FET having a drain connected to said positive terminal, a gate connected to said source of said first FET and a source connected to a bit line; a depletion mode fourth FET having a drain connected to said positive terminal and a gate a source connected to said bit line; a depletion mode fifth FET having a drain connected to said positive terminal and a gate connected to said bit line; a depletion mode sixth FET having a drain connected to said positive terminal; an enhancement mode seventh FET having a drain connected to a source of said fifth FET and a source connected to ground; an enhancement mode eighth FET having a gate and drain connected to a source of said sixth FET and to a gate of said seventh FET, and a source connected to ground; a depletion mode ninth FET having a drain and gate connected to said positive terminal and a source connected to a gate of said sixth FET; a depletion mode tenth FET havin a drain connected to said source of said ninth FET and a gate and source connected ground; a depletion mode eleventh FET having a drain connected to said positive terminal; and an enhancement mode twelfth FET having a drain connected to a source and gate of said eleventh FET, a gate connected to said drain of said seventh FET, and a source connected to ground, an output signal being produced on said drain of said twelfth FET.

Claim 12

The sense amplifier of claim 9 wherein said first and ninth FETs are of the same type and structure and said second and tenth FETs are of the same type and structure.

Claim 13

The sense amplifier of claim 9 wherein said fifth and sixth FETs are of the same type and structure and said seventh and eighth FETs are of the same type and structure.

Claim 14

The sense amplifier of claim 9 wherein said third FET has a substantially greater current driving capability than a data cell connected to said bit line.

Claim 15

The sense amplifier of claim 9 wherein said fourth FET has a threshold voltage such that a breakpoint between a saturation mode and a linear mode of said fourth FET on a current-voltage characteristic curve representative of said fourth FET is at a point on said curve such that a difference between said power supply voltage on said positive terminal and the magnitude of said threshold voltage of said fourth FET is substantially equal to a reference voltage on said gate of said sixth FET.