Method of making high density complementary transistors

Claim 2

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming a well having a P type conductivity in a semiconductor substrate having an N type conductivity, forming first and second N type conductivity regions defining a channel region within said well, forming within said well a P type region having a more positive conductivity than that of said well surrounding said first and second N type conductivity regions and said channel region and having a contact region within said P type conductivity region butted with respect to one of said first and second N type conductivity regions, forming a P channel device having a control electrode and source and drain regions in said semiconductor substrate without said P type well, said source and drain regions being formed simultaneously with said contact region, forming a control electrode over said channel region having a different work function from that of the work function of the control electrode of said P channel device and forming a single electrode in contact with said contact region and said one N type conductivity region.

Claim 3

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 1 wherein said P type conductivity region is spaced from the edge of said P type well.

Claim 4

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 1 further including annealing said first and second N type conductivity regions before forming said P type conductivity region.

Claim 5

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 1 further including the step of simultaneously forming an N type conductivity guardring region in said semiconductor substrate without said P type well with said first and second N type conductivity regions.

Claim 6

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 4 wherein said guardring region is formed prior to the formation of said P type conductivity region.

Claim 7

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an N- type epitaxial layer on an N+ type silicon substrate, forming a well having a P- type conductivity in said epitaxial layer, introducing an N type impurity into said well for forming first and second N+ type conductivity regions defining a channel region within said well, annealing said epitaxial layer to drive in said N type impurity for forming substantially the final profile of said first and second N+ regions, forming a P+ type conductivity region within said P- type well abutting said first and second N+ type conductivity regions and surrounding said channel region, forming a P channel device having a first control electrode in said epitaxial layer without said P- type well, forming a contact on said P+ type conductivity region, and forming a second control electrode over said channel region, said second electrode having a different work function from that of the first control electrode of said P channel device and said contact on said P+ type conductivity region also contacting one of said first and second N+ type conductivity regions.

Claim 8

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an N- type epitaxial layer on an N+ type silicon substrate, forming a well having a P- type conductivity in said epitaxial layer, introducing an N type impurity into said well for forming first and second N+ type conductivity regions defining a channel region within said well, annealing said epitaxial layer to drive in said N type impurity for forming substantially the final profile of said first and second N+ regions, forming a P+ type conductivity region within said P- type well abutting said first and second N+ type conductivity regions and surrounding said channel region, forming a P channel device having a first control electrode in said epitaxial layer without said P- type well, forming a contact on said P+ type conductivity region, and forming a second control electrode over said channel region, said second electrode having a different work function from that of the first control electrode of said P channel device and said contact on said P+ type conductivity region also contacting one of said first and second N+ type conductivity regions.

Claim 9

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 6 wherein said P+ type conductivity region is spaced from the edge of said P- type well.

Claim 10

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 6 further including the step of simultaneously forming an N+ type conductivity guardring region in said N- type epitaxial layer without said P- type well with said first and second N+ type conductivity regions.

Claim 11

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an oxidation barrier layer on a semiconductor substrate of a given conductivity type having first and second portions, forming a well in the first portion of said substrate having a conductivity type opposite to that of said given conductivity type, defining source and drain regions in said well, removing a first portion of said oxidation barrier layer over said source and drain regions, implanting a first impurity of said given conductivity type into said source and drain regions, defining a field region in said well, removing a second portion of said oxidation barrier layer over said field region, implanting a second impurity of said opposite conductivity type into said field region, defining source and drain regions in the second portion of said substrate, removing a third portion of said oxidation barrier layer over said second portion source and drain regions, implanting a third impurity of said opposite conductivity type into said second portion source and drain regions, defining an isolation region in said substrate, removing a fourth portion of said oxidation barrier layer over said isolation region, and oxidizing the surface of said substrate without the remaining portion of said oxidation barrier layer.

Claim 12

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an oxidation barrier layer on a semiconductor substrate of a given conductivity type having first and second portions, forming a well in the first portion of said substrate having a conductivity type opposite to that of said given conductivity type, defining source and drain regions in said well, removing a first portion of said oxidation barrier layer over said source and drain regions, implanting a first impurity of said given conductivity type into said source and drain regions, defining a field region in said well, removing a second portion of said oxidation barrier layer over said field region, implanting a second impurity of said opposite conductivity type into said field region, defining source and drain regions in the second portion of said substrate, removing a third portion of said oxidation barrier layer over said second portion source and drain regions, implanting a third impurity of said opposite conductivity type into said second portion source and drain regions, defining an isolation region in said substrate, removing a fourth portion of said oxidation barrier layer over said isolation region, and oxidizing the surface of said substrate without the remaining portion of said oxidation barrier layer.

Claim 13

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 9 wherein said given conductivity type is N conductivity type and said opposite conductivity type is P conductivity type.

Claim 14

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 9 wherein said source and drain regions are defined by openings in a first photoresist mask and said first impurity is arsenic.

Claim 15

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 11 wherein said field region is defined by openings in a second photoresist mask and said second impurity is boron.

Claim 16

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 12 wherein said third impurity is boron and further including the steps of forming a first control electrode having a given work function between said source and drain regions of said first portion and forming a second control electrode having a work function different from said given work function between said source and drain regions of said second portion.

Claim 17

A process for making a complementary metal oxide semiconductor (CMOS) structure as set forth in claim 13 further including the step of forming a single ohmic contact to said field region and to one of said source and drain regions of said first portion.

Claim 18

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an oxidation barrier layer on a semiconductor substrate of a given conductivity, forming a well having a conductivity opposite to that of said given conductivity in said semiconductor substrate, forming within said well through a first opening in said oxidation barrier layer first and second regions having said given conductivity defining a channel region, forming within said well through a second opening in said oxidation barrier layer a region of opposite conductivity having a higher conductivity than that of said well surrounding said first and second regions and said channel region, forming through a third opening in said oxidation barrier layer source and drain regions in said semiconductor substrate without said well, and oxidizing the surface of said substrate through a fourth opening in said oxidation barrier layer.

Claim 19

A process for making a complementary metal oxide semiconductor (CMOS) structure comprising the steps of: forming an oxidation barrier layer on a semiconductor substrate of a given conductivity, forming a well having a conductivity opposite to that of said given conductivity in said semiconductor substrate, forming within said well through a first opening in said oxidation barrier layer first and second regions having said given conductivity defining a channel region, forming within said well through a second opening in said oxidation barrier layer a region of opposite conductivity having a higher conductivity than that of said well surrounding said first and second regions and said channel region, forming through a third opening in said oxidation barrier layer source and drain regions in said semiconductor substrate without said well, and oxidizing the surface of said substrate through a fourth opening in said oxidation barrier layer.