Patent US4470874A successfully refreshed from Google Patents.
US4470874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planarization of multi-level interconnected metallization system
Assignee: International Business Machines Corp
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Filing: 1983-12-15
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Granted: 1984-09-11
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Expires: 2003-12-15
Abstract
Abstract The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF 4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.
Inventors
- 👤 Thomas A. Bartush
- 👤 Garth A. Brooks
- 👤 James R. Kitcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:30
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/262; H10P50/28; H10P50/282; H10P50/283; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
151 words
A method for fabricating interconnection stud structures on a substrate having formed on an insulated surface thereof a conductive metallic pattern interconnected to internal circuits in said substrate through via openings in said surface comprising: (A) forming at least one conductive vertical stud on said surface; (B) blanket depositing a dielectric layer on said surface to imbed said pattern and said stud; (C) blanket coating a resist layer on said dielectric layer; (D) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric and resist layers, and continuing said etching to remove said resist layer concurrently with planarization of said dielectric layer; and (E) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric layer and said studs, and continuing second said etching to expose the top surface of each said stud in a substantially common plane with said dielectric layer.
Claim 2
Independent Claim
151 words
A method for fabricating interconnection stud structures on a substrate having formed on an insulated surface thereof a conductive metallic pattern interconnected to internal circuits in said substrate through via openings in said surface comprising: (A) forming at least one conductive vertical stud on said surface; (B) blanket depositing a dielectric layer on said surface to imbed said pattern and said stud; (C) blanket coating a resist layer on said dielectric layer; (D) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric and resist layers, and continuing said etching to remove said resist layer concurrently with planarization of said dielectric layer; and (E) dry etching said substrate in an ambient providing substantially equal etch rates for said dielectric layer and said studs, and continuing second said etching to expose the top surface of each said stud in a substantially common plane with said dielectric layer.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein Step A comprises the formation of at least two of said studs having the top surfaces thereof extending in respective vertically displaced planes relative to said surface.
Claim 4
Dependent Claim
22 words
The method of claim 2 wherein said dielectric comprises quartz, and said pattern and each of said studs comprise on aluminum-based alloy.
Claim 5
Dependent Claim
26 words
The method of claim 3 including the step of blanket coating said substrate pattern and each said stud with silicon nitirde between Steps A and B.
Claim 6
Dependent Claim
22 words
The method of claim 1 wherein said dielectric comprises quartz, and said pattern and each of said studs comprises on aluminum-based alloy.
Claim 7
Dependent Claim
26 words
The method of claim 5 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 8
Dependent Claim
26 words
The method of claim 1 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 9
Dependent Claim
18 words
The method of claim 3 wherein the first said etching ambient of step D comprises CF 4 .
Claim 10
Dependent Claim
26 words
The method of claim 8 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 11
Dependent Claim
17 words
The method of claim 8 wherein the second said ambient of Step E is a noble gas.
Claim 12
Dependent Claim
26 words
The method of claim 10 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 13
Dependent Claim
18 words
The method of claim 5 wherein the first said etching ambient of Step D comprises CF 4 .
Claim 14
Dependent Claim
26 words
The method of claim 12 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 15
Dependent Claim
17 words
The method of claim 12 wherein the second said ambient of Step E is a noble gas.
Claim 16
Dependent Claim
26 words
The method of claim 14 including the step of blanket coating said substrate pattern and each said stud with silicon nitride between Steps A and B.
Claim 17
Dependent Claim
13 words
The method of claim 1 wherein said substrate comprises an integrated circuit device.
Claim 18
Dependent Claim
13 words
The method of claim 1 wherein said substrate comprises an integrated circuit device.
Claim 19
Dependent Claim
13 words
The method of claim 2 wherein said substrate comprises an integrated circuit device.
Claim 20
Dependent Claim
13 words
The method of claim 3 wherein said substrate comprises an integrated circuit device.
Claim 21
Dependent Claim
13 words
The method of claim 4 wherein said substrate comprises an integrated circuit device.
Claim 22
Dependent Claim
13 words
The method of claim 5 wherein said substrate comprises an integrated circuit device.
Claim 23
Dependent Claim
13 words
The method of claim 6 wherein said substrate comprises an integrated circuit device.
Claim 24
Dependent Claim
13 words
The method of claim 7 wherein said substrate comprises an integrated circuit device.
Claim 25
Dependent Claim
13 words
The method of claim 8 wherein said substrate comprises an integrated circuit device.
Claim 26
Dependent Claim
13 words
The method of claim 9 wherein said substrate comprises an integrated circuit device.
Claim 27
Dependent Claim
13 words
The method of claim 10 wherein said substrate comprises an integrated circuit device.
Claim 28
Dependent Claim
13 words
The method of claim 11 wherein said substrate comprises an integrated circuit device.
Claim 29
Dependent Claim
13 words
The method of claim 12 wherein said substrate comprises an integrated circuit device.
Claim 30
Dependent Claim
13 words
The method of claim 13 wherein said substrate comprises an integrated circuit device.
Claim 31
Dependent Claim
13 words
The method of claim 14 wherein said substrate comprises an integrated circuit device.
Claim 32
Dependent Claim
13 words
The method of claim 15 wherein said substrate comprises an integrated circuit device.
Claim 33
Dependent Claim
13 words
The method of claim 16 wherein said substrate comprises an integrated circuit device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-11 | 1988-03-12 | 1988-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-11 | 1992-03-12 | 1992-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-11 | 1996-03-12 | 1996-09-11 | $7700.00 | Window Closed / Lapsed |