Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS

Claim 2

A semiconductor integrated circuit device comprising: a semiconductor substrate; field insulating films dividing said substrate into a number of predetermined areas; an MIS type memory array portion including a plurality of MIS type memory transistors disposed in a first one of said areas, said MIS type memory array portion being capable of writing and reading operations under receipt of high and low voltages, respectively; an MIS type peripheral circuit portion formed in said semiconductor substrate outside of said first area in association with said MIS type memory array portion and comprising a plurality of MIS type transistors which are formed at a second of said predetermined areas defined by said field insulating films, said plurality of MIS type transistors including at least first and second types of MIS type transistors which are capable of operating at said high and low voltages, respectively; said first type of MIS type transistors each including first source and drain regions formed in said semiconductor substrate at said second predetermined area, a first gate insulating film extending over the surface portion of said semiconductor substrate between said first source and drain regions and having a substantially flat surface parallel to the underlying surface portion, and a first gate electrode formed on the flat surface of said first gate insulating film, said first gate insulating film having a thickness thinner than that of said field insulating films; and said second type of MIS type transistors each including second source and drain regions formed in said semiconductor substrate at said second predetermined area, a second gate insulating film extending over the surface portion of said semiconductor substrate between said second source and drain regions and having a substantially flat surface parallel to the underlying surface portion, and a second gate electrode formed on the flat surface of said second insulating film, said second gate insulating film having a thickness thinner than that of said first gate insulating film.

Claim 3

A semiconductor integrated circuit device as defined in claim 1, wherein the surface portions of said semiconductor substrate underlying said first gate insulating films of said first type of MIS type transistors have a first impurity concentration and the surface portions of said semiconductor substrate underlying said second gate insulating films of said second type of MIS type transistors have a second inpurity concentration different from said first impurity concentration.

Claim 4

A semiconductor integrated circuit device as defined in claim 1, wherein the surface portions of said semiconductor substrate underlying said first gate insulating films of said first type of MIS type transistors have the same impurity concentration as the surface portions of said semiconductor substrate underlying said second gate insulating films of said second type of MIS type transistors.

Claim 5

A semiconductor integrated circuit device as defined in claim 2, wherein said first impurity concentration is lower than said second impurity concentration so that said first and second types of MIS type transistors have approximately equal threshold voltages to each other.

Claim 6

A semiconductor integrated circuit device as defined in any one of claims 1-3, wherein each of said plurality of MIS type memory transistors has a floating gate electrode formed on a gate insulating film covering a portion of the predetermined area in said first location, and a control gate electrode overlying said floating gate electrode.

Claim 7

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; field insulating films dividing said substrate into a number of predetermined areas; a plurality of MIS type transistors formed in said predetermined areas of said semiconductor substrate, said plurality of MIS type transistors including at least first and second types of enhancement mode transistors which are capable of operating at high and low voltages, respectively; said first type of enhancement mode transistors each including first source and drain regions of a second conductivity type opposite to said first conductivity type formed in said semiconductor substrate at said predetermined areas, a first gate insulating film extending over the surface portion of said semiconductor substrate between said first source and drain regions having a substantially flat surface parallel to the underlying surface portion, and a first gate electrode, formed on the flat surface of said first gate insulating film, for forming a channel region at the surface portion of said semiconductor substrate between said first source and drain regions, said first gate insulating film having a thickness thinner than that of said field insulating films; said second type of enhancement mode transistors each including second source and drain regions of said second conductivity type formed in said semiconductor substrate at the predetermined area, a second gate insulating film extending over the surface portion of said semiconductor substrate between said second source and drain regions and having a substantially flat surface, and a second gate electrode, formed on the flat surface of said second insulating film, for forming a channel region at the surface portion of said semiconductor substrate between said second source and drain regions, said second gate insulating film having a thickness thinner than that of said first gate insulating film; and each of said surface portions serving as the channel regions of said first type of transistors having a first impurity concentration of said first conductivity type, while each of said surface portions serving as the channel regions of said second type of transistors has a second impurity concentration of said first conductivity type higher than said first impurity concentration.

Claim 8

A semiconductor integrated circuit device comprising: a semiconductor substrate of a first conductivity type; field insulating films dividing said substrate into a number of predetermined areas; a plurality of MIS type transistors formed in said predetermined areas of said semiconductor substrate, said plurality of MIS type transistors including at least first and second types of enhancement mode transistors which are capable of operating at high and low voltages, respectively; said first type of enhancement mode transistors each including first source and drain regions of a second conductivity type opposite to said first conductivity type formed in said semiconductor substrate at said predetermined areas, a first gate insulating film extending over the surface portion of said semiconductor substrate between said first source and drain regions having a substantially flat surface parallel to the underlying surface portion, and a first gate electrode, formed on the flat surface of said first gate insulating film, for forming a channel region at the surface portion of said semiconductor substrate between said first source and drain regions, said first gate insulating film having a thickness thinner than that of said field insulating films; said second type of enhancement mode transistors each including second source and drain regions of said second conductivity type formed in said semiconductor substrate at the predetermined area, a second gate insulating film extending over the surface portion of said semiconductor substrate between said second source and drain regions and having a substantially flat surface, and a second gate electrode, formed on the flat surface of said second insulating film, for forming a channel region at the surface portion of said semiconductor substrate between said second source and drain regions, said second gate insulating film having a thickness thinner than that of said first gate insulating film; and each of said surface portions serving as the channel regions of said first type of transistors having a first impurity concentration of said first conductivity type, while each of said surface portions serving as the channel regions of said second type of transistors has a second impurity concentration of said first conductivity type higher than said first impurity concentration.

Claim 9

A semiconductor integrated circuit device as defined in claim 6, wherein sid first and second impurity concentrations are defined so that said first and second types of transistors have enhancement mode threshold voltages approximately equal to each other.

Claim 10

A semiconductor integrated circuit device comprising: a semiconductor substrate having a major surface; a field insulating layer formed on the surface of said substrate and dividing said major surface into plural areas; a first type of enhancement mode MIS transistors formed in ones of said plural areas, said first type of MIS transistors each including a gate insulating film having a thickness thinner than that of said field insulating layer; a second type of enhancement mode MIS transistors formed in others of said plural areas, said second type of MIS transistors each including a gate insulating film each having a thickness thinner than that of said gate insulating film of said first type of MIS transistors; wherein each of the surface portions of said semiconductor substrate underlying the gate insulating films for said first type of MIS transistors has an impurity concentration lower than that of each of the surface portions of said semiconductor substrate underlying the gate insulating films for said second type of MIS transistors thereby defining enhancement mode threshold voltages of both said first and second types of transistors.

Claim 11

A semiconductor integrated circuit device comprising: a semiconductor substrate having a major surface; a field insulating layer formed on the surface of said substrate and dividing said major surface into plural areas; a first type of enhancement mode MIS transistors formed in ones of said plural areas, said first type of MIS transistors each including a gate insulating film having a thickness thinner than that of said field insulating layer; a second type of enhancement mode MIS transistors formed in others of said plural areas, said second type of MIS transistors each including a gate insulating film each having a thickness thinner than that of said gate insulating film of said first type of MIS transistors; wherein each of the surface portions of said semiconductor substrate underlying the gate insulating films for said first type of MIS transistors has an impurity concentration lower than that of each of the surface portions of said semiconductor substrate underlying the gate insulating films for said second type of MIS transistors thereby defining enhancement mode threshold voltages of both said first and second types of transistors.