Clock synchronization signal generating circuit

Claim 2

A clock synchronization signal generating circuit comprising: a source clock generating means; a clock synchronizing circuit including a first frequency dividing means for frequency-dividing a source clock signal from said source clock generating means by a frequency dividing factor of N which is variable in a range of n1≧N≧n2 wherein n1, n2 and N are positive integers and n1>n2, and supplying an output signal to operate a digital operation system in a slave mode and a control means for controlling the frequency dividing factor of said first frequency dividing means to clock-synchronize an output signal of said first frequency dividing means with an input signal according to the phase relation between the output signal of said first frequency dividing means and the input signal; and a clock circuit including a second frequency dividing means for frequency-dividing the source clock signal from said source clock generating means by a predetermined dividing factor of n3 which is set to be substantially in a range of n1>n3>n2, and supplying an output signal to operate said digital operation system in a master mode.

Claim 3

A clock synchronization signal generating circuit according to claim 1 wherein n1 is set to a value larger than (n2+1).

Claim 4

A clock synchronization signal generating circuit according to claim 1 or 2 wherein said first frequency dividing means includes a scale variable counting circuit for counting a source clock signal from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 5

A clock synchronization signal generating circuit according to claim 3 wherein said second frequency dividing means includes an n4-scale counting circuit in which n4 is an integer in a range of n1>n4>n2 and which counts a source clock signal from said source clock generating means, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 6

A clock synchronization signal generating circuit according to claim 4 wherein said scale variable counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means controls the scale of said scale variable counting circuit to be set according to the phase relation between said condition indicating signal and said input signal.

Claim 7

A clock synchronization signal generating circuit according to claim 4 further comprising an inhibit circuit for inhibiting the output signal of said scale variable counting circuit when said scale variable counting circuit comes to have contents different from predetermined counting contents.

Claim 8

A clock synchronization signal generating circuit according to claim 3 wherein said scale variable counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means controls the scale of said scale variable counting circuit to be set according to the phase relation between said condition indicating signal and said input signal.

Claim 9

A clock synchronization signal generating circuit according to claim 3 further comprising an inhibit circuit for inhibiting the output signal of said scale variable counting circuit when said scale variable counting circuit comes to have contents different from predetermined counting contents.

Claim 10

A clock synchronization signal generating circuit according to claim 1 or 2 wherein said first frequency dividing means includes a first counting circuit of n2-scale for counting a source clock signal from said source clock generating means, a circuit for preventing said source clock signal from being supplied to said first counting circuit over an inhibition period of time defined by a control signal from said control means in each of counting cycles in said first counting circuit, and a decoding circuit for decoding an output signal from said first counting circuit.

Claim 11

A clock synchronization signal generating circuit according to claim 9 wherein said second frequency dividing means includes a second counting circuit of n4-scale in which n4 is an integer in a range of n1>n4>n2 and which counts a source clock signal from said source clock generating means, and a decoding circuit for decoding an output signal from said second counting circuit.

Claim 12

A clock synchronization signal generating circuit according to claim 10 wherein said first counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means sets the length of said inhibition period of time to a predetermined value according to the phase relation between said condition indicating signal and said input signal.

Claim 13

A clock synchronization signal generating circuit according to claim 1 wherein n1 is set equal to (n2+1).

Claim 14

A clock synchronization signal generating circuit according to claim 12 wherein said second frequency dividing means includes a first scale variable counting circuit for operating as n3-scale counter counting selectively in n1- or n2-scale mode a source clock signal from said source clock generating means, and a decoding circuit for decoding an output signal of said first counting circuit.

Claim 15

A clock synchronization signal generating circuit according to claim 13 wherein said first frequency dividing means includes a second scale variable counting circuit for counting a source clock signal from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit for decoding an output signal from said second counting circuit.

Claim 16

A clock synchronization signal generating circuit according to claim 14 wherein said second scale variable counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means controls the scale of said second scale variable counting circuit to be set according to the phase relation between said condition indicating signal and said input signal.

Claim 17

A clock synchronization signal generating circuit according to claim 14 further comprising a circuit for preventing the output signal of said second scale variable counting circuit when said second scale variable counting circuit has contents different from predetermined counting contents.

Claim 18

A clock synchronization signal generating circuit according to claim 1 wherein said second frequency dividing means includes a first scale variable counting circuit for operating substantially as n3-scale counter circuit to count selectively in at least two different scales a source clock signal from said source clock generating means, and a decoding circuit for decoding an output signal of said first counting circuit.

Claim 19

A clock synchronization signal generating circuit according to claim 17 wherein said first frequency dividing means includes a second scale variable counting circuit for counting a source clock signal from said source clock generating means and whose scale N is controlled by said control means, and a decoding circuit for decoding an output signal from said second counting circuit.

Claim 20

A clock synchronization signal generating circuit according to claim 18 wherein said second scale variable counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means controls the scale of said second scale variable counting circuit to be set according to the phase relation between said condition indicating signal and said input signal.

Claim 21

A clock synchronization signal generating circuit according to claim 18 further comprising a circuit for preventing an output signal of said second scale variable counting circuit when said second scale variable counting circuit has contents different from predetermined counting contents.

Claim 22

A clock synchronization signal generating circuit comprising: a source clock generating means; a variable frequency dividing means for frequency-dividing a source clock signal from said source clock generating means by a frequency dividing factor of N which is variable in a range of n1>N>n2 wherein n1, n2 and N are positive integers and n1>n2; and a control means for supplying a first control signal to said variable frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than n1, and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal; said variable frequency dividing means includes a scale variable counting circuit for carrying out n4-scale counting operation responsive to the first control signal from said control means in which n4 is an integer in a range of n1>n4>n2 and whose scale N is controlled responsive to the second control signal from said control means, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 23

A clock synchronization signal generating circuit comprising: a source clock generating means; a variable frequency dividing means for frequency-dividing a source clock signal from said source clock generating means by a frequency dividing factor of N which is variable in a range of n1>N>n2 wherein n1, n2 and N are positive integers and n1>n2; and a control means for supplying a first control signal to said variable frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than n1, and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal; said variable frequency dividing means includes a scale variable counting circuit for carrying out n4-scale counting operation responsive to the first control signal from said control means in which n4 is an integer in a range of n1>n4>n2 and whose scale N is controlled responsive to the second control signal from said control means, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 24

A clock synchronization signal generating circuit according to claim 21 wherein said scale variable counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means controls the scale of said scale variable counting circuit in second operation mode to be set according to the phase relation between said condition indicating signal and said input clock signal.

Claim 25

A clock synchronization signal generating circuit according to claim 21 further comprising a circuit for inhibiting the output signal of said scale variable counting circuit when said scale variable counting circuit has contents different from predetermined counting contents.

Claim 26

A clock synchronization signal generating circuit comprising: a source clock generating means; a variable frequency dividing means for frequency-dividing a source clock signal from said source clock generating means by a frequency dividing factor of N which is variable in a range of n1>N>n2 wherein n1, n2 and N are positive integers and n1>n2; and a control means for supplying a first control signal to said variable frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than n1, and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal; said variable frequency dividing means includes a counting circuit of n2-scale for counting a source clock signal from said source clock generating means, a clock preventing circuit for preventing the source clock signal over a first preventing period defined by the first control signal supplied from said control means and over a second preventing period selectively defined by the second control signal supplied from said control means in each of counting cycles in said counting circuit, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 27

A clock synchronization signal generating circuit comprising: a source clock generating means; a variable frequency dividing means for frequency-dividing a source clock signal from said source clock generating means by a frequency dividing factor of N which is variable in a range of n1>N>n2 wherein n1, n2 and N are positive integers and n1>n2; and a control means for supplying a first control signal to said variable frequency dividing means in first operation mode to set the frequency dividing factor of said variable frequency dividing means to a value of n3 larger than n2 but smaller than n1, and for supplying a second control signal to said variable frequency dividing means in second operation mode according to the phase relation between an input clock signal and an output signal from said variable frequency dividing means to control the frequency dividing factor of said variable frequency dividing means to clock-synchronize the output signal of said variable frequency dividing means with the input clock signal; said variable frequency dividing means includes a counting circuit of n2-scale for counting a source clock signal from said source clock generating means, a clock preventing circuit for preventing the source clock signal over a first preventing period defined by the first control signal supplied from said control means and over a second preventing period selectively defined by the second control signal supplied from said control means in each of counting cycles in said counting circuit, and a decoding circuit for decoding an output signal from said counting circuit.

Claim 28

A clock synchronization signal generating circuit according to claim 24 wherein said first counting circuit generates a condition indicating signal when it comes to have a predetermined counting value in each of counting cycles, and said control means sets in second operation mode the length of said preventing period to a predetermined value according to the phase relation between said condition indicating signal and said input clock signal.

Claim 29

A clock synchronization signal generating circuit according to claim 21 or 24 wherein n1 is set to a value larger than (n2+1).