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US4489397A
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Chain configurable polycellular wafer scale integrated circuit
Assignee: Unisys Corp
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Filing: 1984-01-24
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Granted: 1984-12-18
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Expires: 2004-01-24
Abstract
Abstract A digital memory system comprises a wafer full of uncomitted but interconnectable memory cells and a controller acting as an interface between the wafer and a host system. Each cell comprises input logic to allow coupling thereto from just one other neighboring cell and output logic allowing a cell to be commanded by the controller to couple to any selectable one other neighboring cell not already so coupled to. The controller accesses the wafer via a port and successively tests and couples cells from the port to form a chain of memory cells. Each cell comprises a plurality of individually selectably usable data storage loops and allows a cell to be used even if the loops are not fully functional by the provision of through-passing data transfer path.
Inventors
- 👤 Kin H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G11; G11C; G11C29/00; G11C29/006
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
210 words
A wafer scale integrated circuit having a plurality of adjacent data processing cells on a common wafer substrate, the circuit receiving an external synchronizing signal, said cells transfering data and commands between them, said cells comprising: a cell address decoding means receiving said commands, said address decoding means operable to monitor a cell address in each said command and provide an output indicative that said command has reached the cell address; command decoder means receiving said commands for monitoring an indication portion of said command, and responding to the receipt of said output of said cell address decoding means to provide an output indicative of which one out of a plurality of instructions is selected; at least one data processing element coupled to receive the output of said command decoder means and responding to the selected instruction to act upon said data, said data processing element having fixed address storage locations; and, transfer means receiving said data and commands and coupled to provide said data and commands to said cell address decoding means and said command decoder means, said transfer means monitoring the output of said cell address decoding means and responding to the absence of an output to provide functional coupling between neighboring cells for said data and commands.
Claim 2
Dependent Claim
210 words
A wafer scale integrated circuit having a plurality of adjacent data processing cells on a common wafer substrate, the circuit receiving an external synchronizing signal, said cells transfering data and commands between them, said cells comprising: a cell address decoding means receiving said commands, said address decoding means operable to monitor a cell address in each said command and provide an output indicative that said command has reached the cell address; command decoder means receiving said commands for monitoring an indication portion of said command, and responding to the receipt of said output of said cell address decoding means to provide an output indicative of which one out of a plurality of instructions is selected; at least one data processing element coupled to receive the output of said command decoder means and responding to the selected instruction to act upon said data, said data processing element having fixed address storage locations; and, transfer means receiving said data and commands and coupled to provide said data and commands to said cell address decoding means and said command decoder means, said transfer means monitoring the output of said cell address decoding means and responding to the absence of an output to provide functional coupling between neighboring cells for said data and commands.
Claim 3
Dependent Claim
82 words
The apparatus of claim 1 having input logic coupled between the input of said transfer means and a plurality of neighboring cells for functionally coupling with any exclusive one of said plurality of neighboring cells, said input logic transfering said data and commands; and having output logic coupled between the output of said transfer means and a plurality of neighboring cells for functionally coupling with any exclusive one of said plurality of neighboring cells, said output logic transfering said data and commands.
Claim 4
Dependent Claim
51 words
The apparatus of claim 2 having a fast reply line which receives data to be read out from the said data processing elements, said fast reply line coupled to said input logic and output logic of each cell such that data is read directly out through each cell without clocking pulses.
Claim 5
Dependent Claim
37 words
The apparatus of claim 3 including a storage loop address decoder coupled to receive said commands from said transfer means for decoding from said command word a selected address in said at least one data processing element.
Claim 6
Dependent Claim
33 words
The apparatus of claim 4 including storage loop control logic for receiving outputs from said command decoder and said storage loop address decoder to control data entering and leaving said data processing elements.
Claim 7
Dependent Claim
33 words
An integrated circuit according to claim 5 wherein said transfer means is a serial-in, serial-out shift register, which is operable to transfer data and commands between said input logic and said output logic.
Claim 8
Dependent Claim
136 words
An integrated circuit according to claim 6 wherein said transfer means further comprises: a subtractor, coupled intermediately between said serial-in serial-out shift register and said output logic for decrementing the address in any command passing therethrough; an adder, coupled intermediately between said input logic and said serial-in serial-out shift register, coupled to receive said output of said address decoder and operable, in response to the absence of said output from address decoder, to increment the address in a subsequent command; said command words having actual command words and an initial dummy command word having all zeros; whereby, the address in an actual command subsequent to an initial dummy command is decremented by a subtractor in said one neighboring cell and is not re-incremented by said adder upon entry into said at least one of said cells.
Claim 9
Dependent Claim
123 words
An integrated circuit according to claim 7 wherein said address decoder means comprises: an all-zeros detector, coupled to monitor the contents of a first plurality of predetermined locations in said serial-in serial-out shift register and operable to provide an output indicative of said contents of said first plurality of predetermined locations simultaneously being zero; and, an address latch, coupled to receive said output from said all-zeros detector, coupled to receive an external synchronizing signal, and operable in response to the receipt of said external synchronizing signal, to acquire and hold as an output the indication from said output of said all zeros detector, where, said external synchronizing signal is indicative of a complete command having been entered into said serial-in serial-out shift register.
Claim 10
Dependent Claim
96 words
An integrated circuit according to claim 8 wherein said command decoder means comprises: a command decoder, coupled to monitor the contents of a second plurality of locations in said serial-in serial-out shift register, and operable in response thereto to provide and output indicative of an instruction to be obeyed; and, a latch, coupled to receive the same input as said command decoder, coupled to receive said external synchronizing signal, and operable in response to the receipt of said external synchronizing signal to acquire and hold the indication instantly provided as the input to said command decoder.
Claim 11
Dependent Claim
25 words
An integrated circuit according to claim 9 wherein said one or more data processing elements comprises one or more individually addressable data storage shift registers.
Claim 12
Dependent Claim
109 words
An integrated circuit according to claim 10 wherein said one or more data storage shift register loops can select one of: accepting an input data stream from said one neighboring cell from said input logic; storing said input data stream and providing back to said input logic for transfer to said one neighboring cell, previously stored contents which are replaced by said input data stream; cycling previously stored contents from finish to start of a shift register for the re-storing of the previously stored contents, at the same time providing as output to said input logic for transfer to said one neighboring cell, a replica of the re-stored contents.
Claim 13
Dependent Claim
130 words
An integrated circuit according to claim 5 wherein said one or more data processing elements comprises one or more individually addressable data storage shift register loops where each of said one or more data storage shift register can selectably do one of: accepting an intput data stream from said one neighboring cell from said intput logic; storing said input data stream and providing, back to said input logic for transfer to said one neighboring cell, previously stored contents which are replaced by said input data stream; cycling previously stored contents from finish to start of a shift register for the restoring of the previously stored contents, at the same time providing as output to said input logic for transfer to said one neighboring cell, a replica of the re-stored contents.
Claim 14
Dependent Claim
87 words
An integrated circuit according to claim 12 wherein said plurality of cells on said common wafer substrate are laid down in a tessellation on said substrate and wherein said integrated circuit comprises an input/output port for providing external functional coupling to said integrated circuit, said input/output port being formed by the omission of one of the cells from one of the sites of said tessellation, functional coupling being provided from the site where a cell is omitted to at least one abutting cell adjacent to said port.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |