FIFO buffer to cache memory

Claim 1

A data processing system comprising a plurality of units including a central processor unit (CPU), a subordinate processor (SUB), an input/output unit (I/O), a system memory and a common electrical bus coupled to each of the units for providing a path for the transfer of information between any of said units during specified periods of time, the system further comprising: a local bus coupled to the CPU and subordinate processor unit; a cache memory and memory management unit coupled to the local bus; and a bus adapter coupled to the cache memory and memory management unit and to the common electrical bus, the bus adapter comprising: (a) first means coupled to the common electrical bus for monitoring information being transmitted from one of said plurality of units to another; (b) second means coupled to said first means for detecting which information is pertinent to the local bus because it is addressed to a unit on the local bus or it is to be written into the system memory; and (c) third means including a first-in-first out buffer (FIFO) coupled to the common electrical bus and to said second means for intercepting information from the common electrical bus and forwarding only that information which is detected as pertinent to the cache memory and memory management unit.