Patent US4497106A successfully refreshed from Google Patents.
US4497106A
Expired / Lapsed
US
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Semiconductor device and a method of manufacturing the same
Assignee: Fujitsu Ltd
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Filing: 1981-10-28
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Granted: 1985-02-05
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Expires: 2001-10-28
Abstract
Abstract A semiconductor device comprising at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, has an electrode for each region of the bipolar transistor and the MIS FET. Each electrode has the same conductivity type as the corresponding region and is connected to ohmic contact with the surface of the corresponding region.
Inventors
- 👤 Yoshinobu Momma
- 👤 Tsuneo Funatsu
- 👤 Atusi Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:46
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
152 words
A method of manufacturing a semiconductor device having at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, comprising the steps of: (a) forming a base region of the bipolar transistor and source and drain regions of the MIS FET in the semiconductor substrate, the base region having a first conductivity type, the source and drain regions having a second conductivity type which is the opposite of the first conductivity type; (b) forming a gate insulating film of the MIS FET on the semiconductor substrate; (c) forming a window for forming an emitter region of the bipolar transistor; (d) forming a polycrystal semiconductor layer covering at least the emitter window of the bipolar transistor and the gate insulating film; and (e) introducing an impurity through the emitter window into the semiconductor substrate to form the emitter region of the bipolar transistor in the semiconductor substrate.
Claim 2
Independent Claim
152 words
A method of manufacturing a semiconductor device having at least one bipolar transistor and at least one MIS FET integrated in a single semiconductor substrate, comprising the steps of: (a) forming a base region of the bipolar transistor and source and drain regions of the MIS FET in the semiconductor substrate, the base region having a first conductivity type, the source and drain regions having a second conductivity type which is the opposite of the first conductivity type; (b) forming a gate insulating film of the MIS FET on the semiconductor substrate; (c) forming a window for forming an emitter region of the bipolar transistor; (d) forming a polycrystal semiconductor layer covering at least the emitter window of the bipolar transistor and the gate insulating film; and (e) introducing an impurity through the emitter window into the semiconductor substrate to form the emitter region of the bipolar transistor in the semiconductor substrate.
Claim 3
Dependent Claim
37 words
A method as set forth in claim 1, wherein said step (e) comprises forming a phosphosilicate glass layer on at least the portion of the polycrystal semiconductor layer covering the emitter window, and heating the semiconductor device.
Claim 4
Dependent Claim
42 words
A method as set forth in claim 1 or 2, further comprising the step of (f) forming aluminum contacts on the polycrystal semiconductor layer and reacting the aluminum contacts and the polycrystal semiconductor layer at the portions overlying the gate insulating film.
Claim 5
Dependent Claim
34 words
A method as set forth in claim 1 or 2, further comprising the step of (f) forming aluminum contacts on the polycrystal semiconductor layer except for the portions over lying said gate insulating film.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |