US4502014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Coincident pulse cancelling circuit
Assignee: Intersil Corp
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Filing: 1982-11-24
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Granted: 1985-02-26
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Expires: 2002-11-24
Abstract
Abstract A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for producing output pulses corresponding to the pulses on the input lines when there is no coincidence or concurrence of pulses on the two input lines.
Inventors
- 👤 Otto H. Bismarck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:26
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/02; H03K21/026; H03K19/00; H03K19/20; H03K19/21
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
141 words
The combination comprising: first and second inputs each for receiving input pulses; first and second networks coupled to said first and second inputs, respectively, each network including a storage means set to a first state in response to the leading edge of an input pulse at its input, and each network including means responsive to the trailing edge of the input pulse and to its storage means being set to said first state for producing an output pulse at a respective output; and control means, coupled to the storage means of said first and second networks, responsive to the coincident presence of input pulses at said first and second inputs for resetting the storage means to a second state in said first and second networks and preventing the subsequent production of output pulses on the trailing edges of the input pulses.
Claim 2
Dependent Claim
141 words
The combination comprising: first and second inputs each for receiving input pulses; first and second networks coupled to said first and second inputs, respectively, each network including a storage means set to a first state in response to the leading edge of an input pulse at its input, and each network including means responsive to the trailing edge of the input pulse and to its storage means being set to said first state for producing an output pulse at a respective output; and control means, coupled to the storage means of said first and second networks, responsive to the coincident presence of input pulses at said first and second inputs for resetting the storage means to a second state in said first and second networks and preventing the subsequent production of output pulses on the trailing edges of the input pulses.
Claim 3
Dependent Claim
85 words
The combination as claimed in claim 1 wherein the storage means in each one of said first and second networks is a set-reset flip-flop and wherein said means responsive to the trailing edge includes a one-shot circuit having its input coupled to be responsive to the input pulse, for producing said output pulse; and wherein the output of the one-shot is fed back to said storage means for resetting it to said second state following the occurrence of the trailing edge of an input pulse.
Claim 4
Dependent Claim
45 words
The combination as claimed in claim 2 wherein said control means includes means responsive to both the storage means of said first and second networks being set to said first state for resetting both of their storage means and placing them in said second state.
References Cited (Backward Citations)
US3593161A
Cited
US3560859A
Cited
US4109209A
Cited
US4185210A
Cited
US4354124A
Cited
US4398101A
Cited
US4398105A
Cited
US4403193A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-26 | 1988-08-27 | 1989-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-26 | 1992-08-27 | 1993-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-26 | 1996-08-27 | 1997-02-26 | $7700.00 | Window Closed / Lapsed |