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US4527259A
Expired / Lapsed
US
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Semiconductor device having insulated gate type non-volatile semiconductor memory elements
Assignee: NEC Corp
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Filing: 1982-09-20
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Granted: 1985-07-02
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Expires: 2002-09-20
Abstract
Abstract A highly integrated semiconductor device has two or more circuits employing non-volatile memory elements built into the same semiconductor substrate, along with read, write and erase, which may operate independently of each other. The memory includes first and second circuit sections, the first circuit section including a first non-volatile memory which is electrically writable and is erasable by ultra-violet rays, and the second circuit section including a second non-volatile memory which is electrically writable and electrically erasable, but which is not erasable by ultra-violet rays. The first circuit section may be a ROM section and the second circuit section may be a CPU in a microcomputer semiconductor device. The first non-volatile memory elements are preferably FAMOS type elements and the second non-volatile memory elements are preferably MNOS elements or F-N elements.
Inventors
- 👤 Takeshi Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:35
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; G11C16/0408; G11C16/0416; G11C16/0433
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
240 words
A semiconductor processor device comprising a ROM, an input/output circuit, a RAM, and a central processing unit formed on a semiconductor substrate; said ROM including a matrix of memory cells arranged in a plurality of rows and columns, each of said memory cells comprising a first insulated gate type non-volatile semiconductor memory transistor, each of said first memory transistors having a gate electrode connected to a row line, a floating gate electrode, a source region and a drain region, one of said source and drain regions being connected to a column line; means for selectively and electrically writing information in the first memory transistor; means for selectively and electrically reading information from said first memory transistor; and means using ultra-violet rays for erasing information stored in said first memory transistor; said central processing unit having an instruction decoder, said instruction decoder including a matrix of memory cells arranged in a plurality of rows and columns, each of said memory cells comprising at least two insulated gate type transistors, one being a second non-volatile memory transistor and the other being a selection transistor connected in series with said second memory transistor; means for activating the selection transistor in order to select the associated second memory transistor; means for electrically writing information in the selected second memory transistor; means for electrically reading information from the selected second memory transistor; and means for erasing information stored in the selected second memory transistor electrically.
Claim 2
Dependent Claim
240 words
A semiconductor processor device comprising a ROM, an input/output circuit, a RAM, and a central processing unit formed on a semiconductor substrate; said ROM including a matrix of memory cells arranged in a plurality of rows and columns, each of said memory cells comprising a first insulated gate type non-volatile semiconductor memory transistor, each of said first memory transistors having a gate electrode connected to a row line, a floating gate electrode, a source region and a drain region, one of said source and drain regions being connected to a column line; means for selectively and electrically writing information in the first memory transistor; means for selectively and electrically reading information from said first memory transistor; and means using ultra-violet rays for erasing information stored in said first memory transistor; said central processing unit having an instruction decoder, said instruction decoder including a matrix of memory cells arranged in a plurality of rows and columns, each of said memory cells comprising at least two insulated gate type transistors, one being a second non-volatile memory transistor and the other being a selection transistor connected in series with said second memory transistor; means for activating the selection transistor in order to select the associated second memory transistor; means for electrically writing information in the selected second memory transistor; means for electrically reading information from the selected second memory transistor; and means for erasing information stored in the selected second memory transistor electrically.
Claim 3
Dependent Claim
233 words
A semiconductor device comprising a semiconductor substrate; a first circuit section and a second circuit section formed in said substrate; said first circuit section including a matrix of memory cells arranged in a plurality of rows and columns; each of said memory cells comprising of a first insulated gate type non-volatile semiconductor memory transistor, each of said first memory transistors having a gate electrode connected to a row line, a floating gate electrode, a source region and a drain region, one of said source and drain regions being connected to a column line; means for selectively and electrically writing information in the first memory transistor; means for selectively and electrically reading information from said first memory transistor; and means for erasing information stored in said first memory transistor with ultra-violet rays; said second circuit section including a matrix of memory cells arranged in a plurality of rows and columns; each of said memory cells comprising of at least two insulated gate type transistors, one being a second non-volatile memory transistor and the other being a selection transistor connected in series with said second memory transistor; means for activating the selection transistor to select the associated second memory transistor; means for electrically writing information in the selected second memory transistor; means for electrically reading information from the selected second memory transistor; and means for electrically erasing information stored in the selected second memory transistor.
Claim 4
Dependent Claim
233 words
A semiconductor device comprising a semiconductor substrate; a first circuit section and a second circuit section formed in said substrate; said first circuit section including a matrix of memory cells arranged in a plurality of rows and columns; each of said memory cells comprising of a first insulated gate type non-volatile semiconductor memory transistor, each of said first memory transistors having a gate electrode connected to a row line, a floating gate electrode, a source region and a drain region, one of said source and drain regions being connected to a column line; means for selectively and electrically writing information in the first memory transistor; means for selectively and electrically reading information from said first memory transistor; and means for erasing information stored in said first memory transistor with ultra-violet rays; said second circuit section including a matrix of memory cells arranged in a plurality of rows and columns; each of said memory cells comprising of at least two insulated gate type transistors, one being a second non-volatile memory transistor and the other being a selection transistor connected in series with said second memory transistor; means for activating the selection transistor to select the associated second memory transistor; means for electrically writing information in the selected second memory transistor; means for electrically reading information from the selected second memory transistor; and means for electrically erasing information stored in the selected second memory transistor.
Claim 5
Dependent Claim
49 words
A semiconductor device of claim 2, in which said second non-volatile semiconductor memory transistor is an MNOS transistor of a type which stores carriers at a boundary surface between a silicon oxide film formed on said semiconductor substrate and a silicon nitride film formed on said silicon oxide film.
Claim 6
Dependent Claim
47 words
A semiconductor device of claim 2, in which said second non-volatile semiconductor memory transistor is of a type that electrical writing and electrical erasing are effected by making carriers pass through a thin portion of an oxide film under a floating gate electrode by utilizing Fowler-Nordheim tunnels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |