Timing extraction circuit

Claim 2

A timing extraction circuit comprising: a data input terminal for receiving a digital data signal of one selected RZ or NRZ line code; a clock output terminal to which a timing signal is supplied; phase comparing means for dividing a pulse of said digital data signal into leading and following portions in response to said timing signal fed back from said clock output terminal and for producing first and second difference signals having variable pulse durations respectively corresponding to the pulse widths of said leading and following portions; and control means for generating a phase error signal corresponding to the difference between the pulse durations of said first and second difference signals; and variable frequency oscillating means for supplying a timing signal to said clock output terminal, the period of said timing signal being controlled in accordance with said phase error signal to decrease the difference in pulse width between said leading and following portions.

Claim 3

A timing extraction circuit according to claim 1, wherein said phase comparing means includes: first register means for holding a logic value of said digital data signal in response to the leading edge of said timing signal; second register means for holding a logic value of the output signal from said first register means in response to the trailing edge of said timing signal; and first and second logic gate circuits for generating said first and said second difference signals in accordance with said digital data signal, the output signals of said first and second register means, and said timing signal.

Claim 4

A timing extraction circuit according to claim 2, wherein said first register means includes a first D-type flip-flop having a D-input terminal connected to said data input terminal and a clock input terminal connected to the output terminal of said variable frequency oscillating means; said second register means include a first inverter and a second D-type flip-flop having a clock input terminal connected to said output terminal of said variable frequency oscillating means through said first inverter and a D-input terminal supplied with an output signal of said first D-type flip-flop: said first logic gate circuit includes a second inverter and a first NOR gate having a first input terminal connected to said data input terminal through said second inverter, a second input terminal connected to the output terminal of said first D-type flip-flop, a third input terminal connected to the output terminal of said variable frequency oscillating means, and a fourth input terminal connected to the output terminal of said second D-type flip-flop; and said second logic data circuit includes a second NOR gate having a first input terminal connected to said data input terminal through said second inverter, a second input terminal connected to the inverted output terminal of said first D-type flip-flop, a third input terminal connected to the output terminal of said variable frequency oscillating means through said first inverter, and a fourth input terminal connected to the output terminal of said second D-type flip-flop circuit.

Claim 5

A timing extraction circuit according to claim 2, wherein said control means includes first and second integrators for integrating said respective first and second difference signals, and phase error detecting means for generating said phase error signal in accordance with the difference between the output signals of said first and second integrators.

Claim 6

A timing extraction circuit according to claim 4, wherein said phase error detecting means includes a subtractor for producing an output signal corresponding to a difference between the output signals of said first and second integrators, and a low-pass filter for integrating the output signal from said subtractor to produce the phase error signal.

Claim 7

A timing extraction circuit according to claim 1, wherein said variable frequency oscillating means is a voltage controlled oscillator.

Claim 8

A timing extraction circuit comprising: a data input terminal for receiving a digital data signal of one selected RZ or NRZ line code; a clock output terminal to which a timing signal is supplied; phase comparing means for dividing a pulse of said digital data signal into leading and following portions in response to said timing signal fed back from said clock output terminal and for producing a first difference signal having a variable pulse duration corresponding to the sum of the period of said leading portion and a period proportional to that of the pulse of said digital data signal and, a second difference signal having a variable pulse duration corresponding to the sum of a pulse duration of said timing signal and said period proportional to that of the pulse of said digital data signal; control means for generating a phase error signal corresponding to the difference between the pulse durations of said first and second difference signals; and variable frequency oscillating means for supplying a timing signal to said clock output terminal, the period of said timing signal being controlled in accordance with said phase error signal to decrease the difference in pulse width between said leading and following portions.

Claim 9

A timing extraction circuit comprising: a data input terminal for receiving a digital data signal of one selected RZ or NRZ line code; a clock output terminal to which a timing signal is supplied; phase comparing means for dividing a pulse of said digital data signal into leading and following portions in response to said timing signal fed back from said clock output terminal and for producing a first difference signal having a variable pulse duration corresponding to the sum of the period of said leading portion and a period proportional to that of the pulse of said digital data signal and, a second difference signal having a variable pulse duration corresponding to the sum of a pulse duration of said timing signal and said period proportional to that of the pulse of said digital data signal; control means for generating a phase error signal corresponding to the difference between the pulse durations of said first and second difference signals; and variable frequency oscillating means for supplying a timing signal to said clock output terminal, the period of said timing signal being controlled in accordance with said phase error signal to decrease the difference in pulse width between said leading and following portions.

Claim 10

A timing extraction circuit according to claim 7, wherein said phase comparing means includes: a first register means for holding a logic value of said digital signal in response to the leading edge of said timing signal; a second register means for holding a logic value of the output signal in response to the trailing edge of said timing signal; a first logic gate for generating said first difference signal in accordance with said digital data signal and the output signal of said first register means; and a second logic gate circuit for generating said second difference signal in accordance with the output signals of said first and second register means.

Claim 11

A timing extraction circuit according to claim 8, wherein said first register means includes: a first D-type flip-flop having a D-input terminal connected to said data input terminal and a clock input terminal connected to the output terminal of said variable frequency oscillating means; said second register means includes a first inverter and a second D-type flip-flop having a clock input terminal connected to the output terminal of said variable frequency oscillating means through said first inverter and a D-input terminal supplied with an output signal of said first D-type flip flop; said first logic gate circuit includes a first OR gate having a first input terminal connected to said data input terminal and second input terminal connected to the output terminal of said first D-type flip-flop; and said second logic gate circuit includes a second OR gate having a first and second input terminal respectively supplied with output signals of said first and second D-type flip-flops.

Claim 12

A timing extraction circuit according to claim 8, wherein said control means includes first and second integrators for integrating said respective first and second difference signals, and phase error detecting means for generating a phase error signal in accordance with the difference between the output signals of said first and second integrators.

Claim 13

A timing extraction circuit according to claim 10, wherein said phase error detecting means includes a subtracter for producing the difference between the output signals from said first and second integrators and a low-pass filter for integrating the signal of said subtractor to produce the phase error signal.

Claim 14

A timing extraction circuit according to claim 7, wherein said variable frequency oscillating means is a voltage controlled oscillator.