US4536718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Jitter reduction circuit for frequency synthesizer
Assignee: US Philips Corp
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Filing: 1983-01-31
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Granted: 1985-08-20
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Expires: 2003-01-31
Abstract
Abstract A frequency synthesizer of the type employing a cycle cancellation technique and providing a correction signal which at least reduces the jitter in the output frequency caused by each cancelled cycle. A control device (CD) causes cycles to be added (PA) and cancelled (PS) without affecting the average frequency (Fc). A compensation signal for the resultant jitter is also generated (DAC and I) which is combined with the correction signal in an adder (AS) and with the frequency control voltage signal from the phase comparator (PC) in a further adder (ASD).
Inventors
- 👤 Michael J. Underhill
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:29
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976; H03L7/1978
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
A frequency synthesizer comprising a reference frequency generator, a frequency control circuit which includes programmable frequency reduction means comprising a cycle cancellation circuit arranged to cancel a cycle of a frequency to be reduced by the frequency reduction means for each input pulse to said cancellation circuit from a pulse source, and a jitter compensation signal circuit connected to the frequency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency of the synthesizer that would otherwise be caused as a result of each cancelled cycle, characterised in that the synthesizer further includes a control device the control signal output of which is arranged to cause the frequency control circuit to cancel cycles from, and also to add cycles to, the frequency to be reduced at a given combined rate, and a control signal compensation circuit connected to the control device and arranged to produce an output signal which is a function of the control signal, the output of the control signal compensation circuit being so connected in the synthesizer circuit as to compensate for any jitter in the output frequency of the synthesizer that would otherwise be caused by the control signal.
Claim 2
Dependent Claim
211 words
A frequency synthesizer comprising a reference frequency generator, a frequency control circuit which includes programmable frequency reduction means comprising a cycle cancellation circuit arranged to cancel a cycle of a frequency to be reduced by the frequency reduction means for each input pulse to said cancellation circuit from a pulse source, and a jitter compensation signal circuit connected to the frequency control circuit, the output signal of the jitter compensation signal circuit being arranged to compensate, at least partly, for any jitter in the period of the output frequency of the synthesizer that would otherwise be caused as a result of each cancelled cycle, characterised in that the synthesizer further includes a control device the control signal output of which is arranged to cause the frequency control circuit to cancel cycles from, and also to add cycles to, the frequency to be reduced at a given combined rate, and a control signal compensation circuit connected to the control device and arranged to produce an output signal which is a function of the control signal, the output of the control signal compensation circuit being so connected in the synthesizer circuit as to compensate for any jitter in the output frequency of the synthesizer that would otherwise be caused by the control signal.
Claim 3
Dependent Claim
39 words
A frequency synthesizer as claimed in claim 1, wherein the number of cycles added by the control signal in a given period is substantially the same as the number of cycles cancelled by the control signal in that period.
Claim 4
Dependent Claim
67 words
A frequency synthesizer as claimed in claim 1 or 2, wherein the control device is so arranged that the control signal comprises at least first and second interspersed pulse sequences, the arrangement being such that each pulse of the first sequence causes a cycle to be cancelled from, and each pulse of the second sequence causes a cycle to be added to, the frequency to be reduced.
Claim 5
Dependent Claim
17 words
A frequency synthesizer as claimed in claim 3, wherein the two sequences together form a pseudo-random sequence.
Claim 6
Dependent Claim
16 words
A frequency synthesizer as claimed in claim 2, wherein the control signal has a Manchester-coded form.
Claim 7
Dependent Claim
17 words
A frequency synthesizer as claimed in claim 2, wherein the control signal is a differentiated code signal.
Claim 8
Dependent Claim
28 words
A frequency synthesizer as claimed in claim 1, including means for combining the outputs of the jitter and control signal compensation circuits to form a combined compensation signal.
Claim 9
Dependent Claim
59 words
A frequency synthesizer as claimed in claim 1, including a detector arranged to detect any residual jitter in the circuit after the application of said combined compensation signal, and a variable gain amplifier arranged to control the amplitude of the combined compensation signal, the gain of the amplifier being controlled by the detector to reduce any said residual jitter.
Claim 10
Dependent Claim
32 words
A frequency synthesizer as claimed in claim 1, wherein the said given combined rate is between one-twentieth and three times the maximum pulse repetition rate of pulses provided by the pulse source.
Claim 11
Dependent Claim
38 words
A frequency synthesizer as claimed in claim 9, wherein the pulse source is a rate multiplier and the given combined rate is equal to the pulse repetition rate of pulses fed to the input of the rate multiplier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |