Patent US4546366A successfully refreshed from Google Patents.
US4546366A
Expired / Lapsed
US
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Polysilicon/silicon junction field effect transistors and integrated circuits (POSFET)
Assignee: Individual
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Filing: 1982-02-19
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Granted: 1985-10-08
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Expires: 2002-02-19
Abstract
Abstract A junction field effect transistor is fabricated in crystalline silicon by using oppositely doped polysilicon as the gate (POSFET). The depletion region of the pn (or np) junction formed at the polysilicon/silicon interface is used as the gate electrode to modulate the current path through the silicon channel from source to drain, the source and drain contacts may either be conventional metal or polysilicon heavily doped of the same conductivity type as the single crystal silicon substrate.
Inventors
- 👤 Bobby L. Buchanan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:29
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/602; H10D30/00; H10D30/80; H10D30/83; H10D62/00; H10D62/10; H10D62/17; H10D62/343
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
A junction field effect transistor for use with large scale integrated circuits having at least one set of source, drain and gate components comprising: a bounding substrate; an overlay substrate having a given conductivity type overlying the bounding substrate; a planar layer of insulative material overlying and contacting the overlay substrate and having formed therein apertures for receiving source, drain and gate material; polysilicon gate material of an opposite conductivity type than said overlay substrate filling said gate aperture and overlying the overlay substrate forming a p-n junction at the interface; conductive material filling the source and drain apertures; and electrical contacts for connecting the source, drain and gate components to an electrical circuit, wherein the insulative material is polysilicon, the gate component is formed of polysilicon doped in the conductivity type opposite that of the overlay substrate material and source and drain components are formed of polysilicon doped in the conductivity type similar to that of the overlay substrate.
Claim 2
Dependent Claim
160 words
A junction field effect transistor for use with large scale integrated circuits having at least one set of source, drain and gate components comprising: a bounding substrate; an overlay substrate having a given conductivity type overlying the bounding substrate; a planar layer of insulative material overlying and contacting the overlay substrate and having formed therein apertures for receiving source, drain and gate material; polysilicon gate material of an opposite conductivity type than said overlay substrate filling said gate aperture and overlying the overlay substrate forming a p-n junction at the interface; conductive material filling the source and drain apertures; and electrical contacts for connecting the source, drain and gate components to an electrical circuit, wherein the insulative material is polysilicon, the gate component is formed of polysilicon doped in the conductivity type opposite that of the overlay substrate material and source and drain components are formed of polysilicon doped in the conductivity type similar to that of the overlay substrate.
Claim 3
Dependent Claim
153 words
A junction field effect transistor for use with large scale integrated circuits having at least one set of source, drain and gate components comprising: a bounding substrate; an overlay substrate having a given conductivity type overlying the bounding substrate; a planar layer of insulative material overlying and contacting the overlay substrate and having formed therein apertures for receiving source, drain and gate material; polysilicon gate material of an opposite conductivity type than said overlay substrate filling said gate aperture and overlying the overlay substrate forming a p-n junction at the interface; conductive material filling the source and drain apertures; and electrical contacts for connecting the source, drain and gate components to an electrical circuit, and wherein said bounding substrate is n type silicon, said overlay substrate is p type silicon, said gate material is heavily doped n+ polysilicon and said conductive material is aluminum, and said layer of insulative material is undoped polysilicon.
Claim 4
Dependent Claim
153 words
A junction field effect transistor for use with large scale integrated circuits having at least one set of source, drain and gate components comprising: a bounding substrate; an overlay substrate having a given conductivity type overlying the bounding substrate; a planar layer of insulative material overlying and contacting the overlay substrate and having formed therein apertures for receiving source, drain and gate material; polysilicon gate material of an opposite conductivity type than said overlay substrate filling said gate aperture and overlying the overlay substrate forming a p-n junction at the interface; conductive material filling the source and drain apertures; and electrical contacts for connecting the source, drain and gate components to an electrical circuit, and wherein said bounding substrate is n type silicon, said overlay substrate is p type silicon, said gate material is heavily doped n+ polysilicon and said conductive material is aluminum, and said layer of insulative material is undoped polysilicon.
Claim 5
Dependent Claim
27 words
A junction field effect transistor as defined in claim 1 wherein said gate material is n type polysilicon doped to approximately 10 19 donors per cubic centimeter.
Claim 6
Dependent Claim
19 words
A junction field effect transistor as defined in claim 1 wherein said overlay substrate is p type crystalline silicon.
Claim 7
Dependent Claim
16 words
A junction field effect transistor as defined in claim 1 wherein said bounding substrate is sapphire.
References Cited (Backward Citations)
US3847687A
Cited
US4176372A
Cited
US4124933A
Cited
US4072974A
Cited
US4072545A
Cited
US4065782A
Cited
US4187514A
Cited
US4231051A
Cited
US4222164A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |