Self-aligned gate method for making MESFET semiconductor

Claim 1

A method for fabrication of a MESFET device in which the gate is self-aligned in relation to the source/drain regions of said device, comprising the steps of: growing a layer of silicon oxide on a silicon substrate of p type conductivity; depositing a layer of heavily doped polysilicon over said layer of silicon oxide; depositing a layer of insulating material over said polysilicon; masking of the area to be the gate region of said device; etching anisotropically to remove all material down to said silicon substrate; oxidizing the structure in a low temperature steam environment to form an oxide layer on exposed areas of said silicon substrate except in said gate region and said polysilicon; implanting N-type impurity through the oxide grown in the previous step and into the substrate to form N+ source and drain regions; removing said insulating material over said polysilicon then removing said polysilicon; etching the structure with an anisotropic plasma etch; implanting an n type impurity in the gate area between the remaining vertical sections of oxide to form an active channel for said MESFET device; depositing a layer of metal over the surface of the structure, and heating to convert the metal to metal silicide where the metal is in contact with said silicon substrate; etching away metal where not converted to metal silicide.

Claim 2

A method for fabrication of a MESFET device in which the gate is self-aligned in relation to the source/drain regions of said device, comprising the steps of: growing a layer of silicon oxide on a silicon substrate of p type conductivity; depositing a layer of heavily doped polysilicon over said layer of silicon oxide; depositing a layer of insulating material over said polysilicon; masking of the area to be the gate region of said device; etching anisotropically to remove all material down to said silicon substrate; oxidizing the structure in a low temperature steam environment to form an oxide layer on exposed areas of said silicon substrate except in said gate region and said polysilicon; implanting N-type impurity through the oxide grown in the previous step and into the substrate to form N+ source and drain regions; removing said insulating material over said polysilicon then removing said polysilicon; etching the structure with an anisotropic plasma etch; implanting an n type impurity in the gate area between the remaining vertical sections of oxide to form an active channel for said MESFET device; depositing a layer of metal over the surface of the structure, and heating to convert the metal to metal silicide where the metal is in contact with said silicon substrate; etching away metal where not converted to metal silicide.