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US4567641A
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Method of fabricating semiconductor devices having a diffused region of reduced length
Assignee: Fairchild Semiconductor Corp
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Filing: 1984-09-12
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Granted: 1986-02-04
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Expires: 2004-09-12
Abstract
Abstract An improved semiconductor device having a diffused region of reduced length and an improved method of fabricating such a semiconductor device are disclosed. The semiconductor device may be a MOSFET or an IGR, by way of example. In a form of the method of fabricating a MOSFET, an N + SOURCE is diffused into a P BASE through a window of a diffusion mask. An anisotropic or directional etchant is applied to the N + SOURCE through the same window. The etchant removes most of the N + SOURCE, but allows shoulders thereof to remain intact. These shoulders, which form the completed N + SOURCE regions, are of reduced length, greatly reducing the risk of turn-on of a parasitic bipolar transistor in the MOSFET. The risk of turn-on of a parasitic bipolar transistor in an IGR is similarly reduced, when the IGR is fabricated by the improved method.
Inventors
- 👤 Bantval J. Baliga
- 👤 Peter V. Gray
- 👤 Robert P. Love
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/038; H10D12/411; H10D12/441; H10D12/461; H10D12/481; H10D30/668; H10D62/00; H10D62/10; H10D62/17; H10D62/393; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P50/69; H10P50/691; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/2527; H10D64/256; H10D64/60; H10D64/66; H10D64/667; H10D64/668
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
129 words
In a method of fabricating a semiconductor device of the type wherein a mask, defining a window, is applied to a major surface of a semiconductor body, and a first region of one dopant type is formed in a second region of opposite dopant type in said body by diffusing a dopant of said one type into said body through said window, with said mask serving as a diffusion barrier, the improvement comprising: anisotropically etching into said body through said window, with said mask serving as an etch barrier; said etch penetrating at least substantially all the way through said first region but allowing shoulders of said first region to remain intact; and forming a short in contact with at least a portion of said first and second regions.
Claim 2
Dependent Claim
129 words
In a method of fabricating a semiconductor device of the type wherein a mask, defining a window, is applied to a major surface of a semiconductor body, and a first region of one dopant type is formed in a second region of opposite dopant type in said body by diffusing a dopant of said one type into said body through said window, with said mask serving as a diffusion barrier, the improvement comprising: anisotropically etching into said body through said window, with said mask serving as an etch barrier; said etch penetrating at least substantially all the way through said first region but allowing shoulders of said first region to remain intact; and forming a short in contact with at least a portion of said first and second regions.
Claim 3
Dependent Claim
39 words
A method of fabricating a semiconductor device in accordance with claim 1 wherein said first region and said short are doped to a high level of conductivity to establish a tunnel junction between said short and said first region.
Claim 4
Dependent Claim
21 words
A method of fabricating a semiconductor device in accordance with claim 1 wherein said short is formed in said major surface.
Claim 5
Dependent Claim
53 words
A method of fabricating a semiconductor device in accordance with claim 1 wherein said etch penetrating at least substantially all the way through said first region, establishes a cut surface through said first and second regions and said short is formed in contact with said cut surface through said first and second regions.
Claim 6
Dependent Claim
18 words
The invention according to claim 1 wherein said semiconductor body comprises a substrate with an epitaxial layer thereon.
Claim 7
Dependent Claim
20 words
The invention according to claim 5 wherein said substrate comprises a DRAIN of a MOSFET of said one dopant type.
Claim 8
Dependent Claim
22 words
The invention according to claim 5 wherein said substrate comprises a region of an insulated gate rectifier of said opposite dopant type.
Claim 9
Dependent Claim
29 words
The invention according to claim 1 wherein said mask comprises conductive refractory material and an oxide of said semiconductor body, said oxide insulating said refractory material from said body.
Claim 10
Dependent Claim
13 words
The invention according to claim 1 wherein said one dopant type comprises N-type.
Claim 11
Dependent Claim
12 words
The invention according to claim 9 wherein said semiconductor body comprises silicon.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |