Decision feedback equalizing apparatus

Claim 3

The method of claim 1 comprising in addition the step of: time delaying said third signal by amounts equivalent to a multiple of the one data bit time delay to produce multiple delayed signals in addition to said fourth signal; and summing said multiple delayed signals with said second and fourth signals to form said composite signal.

Claim 4

Apparatus for equalizing a digital data bit stream comprising, in combination: level detecting first means for enhancing the logic level of the present bit in a digital data bit stream through the use of a substantially non-time delayed positive decision feedback signal obtained through level detection of the present bit in the data bit stream; and second means for neutralizing intersymbol interference on the present bit, the interference being due to previous bit pulse widening, by delaying a signal, obtained from said first means as generated through level detection and of a phase opposite said positive feedback signal, by a time corresponding to its time of occurrence relative the present bit and applying the delayed signal in a feedback manner to the digital bit stream simultaneous with the positive feedback signal.

Claim 5

Apparatus for equalizing a digital data bit stream comprising, in combination: level detecting first means for enhancing the logic level of the present bit in a digital data bit stream through the use of a substantially non-time delayed positive decision feedback signal obtained through level detection of the present bit in the data bit stream; and second means for neutralizing intersymbol interference on the present bit, the interference being due to previous bit pulse widening, by delaying a signal, obtained from said first means as generated through level detection and of a phase opposite said positive feedback signal, by a time corresponding to its time of occurrence relative the present bit and applying the delayed signal in a feedback manner to the digital bit stream simultaneous with the positive feedback signal.

Claim 10

Apparatus for equalizing a digital data bit in a digital signal stream comprising, in combination level detecting first means for detecting a summed first signal to be equalized and outputting a positive feedback and further square pulse opposite phase second and third signals respectively each indicative in polarity of the value of said first signal relative a reference; time delaying second means, connected to said first means, for delaying said third signal by an amount equivalent to the repetition rate for one data bit to produce a delayed fourth signal; summing third means, connected to said first and second means, for summing said second and fourth signals in a weighted algorithm to produce a composite feedback signal; signal input fourth means for supplying a fifth signal to be equalized; and summing fifth means, connected to said first, third and fourth means, for summing said composite feedback signal with a digital pulse signal to be equalized to produce said summed first signal, said summed first signal providing equalized output information.

Claim 11

Apparatus for equalizing a digital data bit in a digital signal stream comprising, in combination level detecting first means for detecting a summed first signal to be equalized and outputting a positive feedback and further square pulse opposite phase second and third signals respectively each indicative in polarity of the value of said first signal relative a reference; time delaying second means, connected to said first means, for delaying said third signal by an amount equivalent to the repetition rate for one data bit to produce a delayed fourth signal; summing third means, connected to said first and second means, for summing said second and fourth signals in a weighted algorithm to produce a composite feedback signal; signal input fourth means for supplying a fifth signal to be equalized; and summing fifth means, connected to said first, third and fourth means, for summing said composite feedback signal with a digital pulse signal to be equalized to produce said summed first signal, said summed first signal providing equalized output information.

Claim 12

Apparatus as claimed in claim 6 and comprising in addition: time delaying sixth means for delaying said third signal by amounts equivalent to a multiple of the time between adjacent bits for one data bit to produce multiple delayed signals in addition to said fourth signal; and seventh means, acting in conjunction with said third means, for summing said multiple delayed signals with said second and fourth signals to form said composite signal.

Claim 15

Apparatus for equalizing a digital data bit stream comprising in combination: first means for supplying a digital data bit stream to be equalized; level detecting second means, connected to said first means for receiving said bit stream therefrom, for providing a positive decision feedback signal, for enhancing the logic level of the present bit in said digital data bit stream, obtained through level detection of the present bit in the data bit stream; level detecting third means, connected to said first means, for providing a further feedback signal, for neutralizing intersymbol interference on the present bit, by delaying a signal, obtained through level detection and of a phase opposite said positive decision feedback signal, by a time corresponding to its time of occurrence relative the present bit; and fourth means, connected to said second and third means, for summing said positive decision and further feedback signals and applying same in a feedback manner to the digital bit stream to be equalized.

Claim 16

Apparatus for equalizing a digital data bit stream comprising in combination: first means for supplying a digital data bit stream to be equalized; level detecting second means, connected to said first means for receiving said bit stream therefrom, for providing a positive decision feedback signal, for enhancing the logic level of the present bit in said digital data bit stream, obtained through level detection of the present bit in the data bit stream; level detecting third means, connected to said first means, for providing a further feedback signal, for neutralizing intersymbol interference on the present bit, by delaying a signal, obtained through level detection and of a phase opposite said positive decision feedback signal, by a time corresponding to its time of occurrence relative the present bit; and fourth means, connected to said second and third means, for summing said positive decision and further feedback signals and applying same in a feedback manner to the digital bit stream to be equalized.

Claim 17

Apparatus for non-linearly equalizing a digital bit pulse stream commprising, in combination: first means for generating a substantially non-time delayed logical level based desision feedback first signal based on the amplitude of the present bit for enhancing the amplitude of the present bit in a digital bit pulse stream; second means for generating a time delayed logical level based decision feedback second signal for reducing intersymbol interference; and third means for combining said first and second signals and incorporating them in a feedback manner with the digital bit pulse stream to modify the characteristics thereof.

Claim 18

Apparatus for non-linearly equalizing a digital bit pulse stream commprising, in combination: first means for generating a substantially non-time delayed logical level based desision feedback first signal based on the amplitude of the present bit for enhancing the amplitude of the present bit in a digital bit pulse stream; second means for generating a time delayed logical level based decision feedback second signal for reducing intersymbol interference; and third means for combining said first and second signals and incorporating them in a feedback manner with the digital bit pulse stream to modify the characteristics thereof.

Claim 19

Apparatus as claimed in claim 10 wherein said third means includes single pole filtering means for modifying the characteristics of the signal passing therethrough whereby said digital bit pulse stream has a raised cosine frequency spectrum.

Claim 20

Apparatus for restoring pulse amplitude during decision processing delayed feedback intersymbol interference equalization of a digital pulse bit stream comprising, in combination: first means for logic level decision detecting the amplitude of the present bit in a pulse bit stream; and second means for generating a square pulse first signal in accordance with said detection; third means for returning said first signal, as a positive decision feedback signal, to the pulse bit stream without any substantial time delay to enhance present bit amplitude.

Claim 21

Apparatus for restoring pulse amplitude during decision processing delayed feedback intersymbol interference equalization of a digital pulse bit stream comprising, in combination: first means for logic level decision detecting the amplitude of the present bit in a pulse bit stream; and second means for generating a square pulse first signal in accordance with said detection; third means for returning said first signal, as a positive decision feedback signal, to the pulse bit stream without any substantial time delay to enhance present bit amplitude.