Twin well single mask CMOS process

Claim 2

A process for forming a self-aligned twin-well structure comprising: providing a substrate layer of predetermined conductivity type; forming a first mask structure on the substrate which is the complement of a first well region; depositing selected impurities in the first region in the presence of the mask structure; depositing a relatively conformal dielectric layer on the resulting structure including the mask, a stressed dielectric layer over the mask sidewall, and first well region using a deposition temperature which is below the flow point of the existing first mask structure; selectively removing the stressed dielectric layer on the mask sidewall; removing the existing first mask structure and the overlying regions of the dielectric layer to form the dielectric layer into a second mask which defines a second well region self-aligned with and the complement of the first well; and depositing impurities in the second well in the presence of the second mask, using impurities of the opposite conductivity type to the first well.

Claim 3

The self-aligned twin-well process of claim 1 wherein the first mask is photoresist.

Claim 4

The self-aligned twin-well process of claim 1 wherein the first mask structure includes an outer layer of photoresist which is removed after the step of depositing impurities for the first well.

Claim 5

The self-aligned twin-well process of claim 1 wherein the first mask structure includes an inner, silicon nitride layer, and an outer, photoresist layer which is removed prior to the step of depositing impurities for the first well.

Claim 6

The self-aligned twin-well process of claim 1, 2, 3 or 4 wherein the first well is formed by ion implantation.

Claim 7

The self-aligned twin-well process of claim 1, 2, 3 or 4 wherein the dielectric layer is silicon oxide.

Claim 8

The process of claim 6 wherein selectively removing the oxide layer on the mask sidewall comprises etching the stressed sidewall oxide layer in buffered HF etchant, and is followed by a removal of the photoresist using ultrasonically agitated acetone to simultaneously remove the overlying oxide.

Claim 9

The self-aligned twin-well process of claim 3 wherein the first mask is formed by growing a stress relief oxide layer on the substrate, forming a layer of silicon nitride which serves as the first mask on the oxide layer, forming a photoresist layer on the silicon nitride and selectively removing corresponding portions of the layers.

Claim 10

The self-aligned twin-well process of claim 8 wherein the first mask removal step comprises etching the dielectric layer from the vertical sidewall sections of the silicon nitride using an HF etchant, then applying hot phosphoric acid to remove the nitride and overlying photoresist from the second well regions.

Claim 11

The self-aligned twin-well process of claim 1, 2, 3 or 4 wherein the secohd well is formed by ion implantation.

Claim 12

The self-aligned twin-well process of claim 7 wherein prior to the step of depositing the second well impurities, the structure is heated to drive in the first well impurities.

Claim 13

The self-aligned twin-well process of claim 8 or 9 wherein prior to the step of depositing the second well impurities, the structure is heated to drive in the first well impurities.

Claim 14

A process for forming a self-aligned twin-well structure comprising: providing a substrate layer of predetermined conductivity type; forming a first mask structure on the substrate comprising a first silicon nitride layer and an outer photoresist layer, which structure is the complement of a first well region; depositing selected impurities in the first well region in the presence of the mask; removing the photoresist layer; depositing a relatively conformal dielectric layer on the resulting structure including the silicon nitride, a stressed dielectric layer over the silicon nitride sidewall, and the first well regions using a deposition temperature which is below the flow point of the silicon nitride; selectively removing the stressed dielectric layer on the silicon nitride sidewall; removing the silicon nitride and the overlying regions of the dielectric layer to form the dielectric into a second mask which defines a second well region self-aligned with the complement of the first well; depositing impurities in the second well in the presence of the second mask, using impurities of the opposite conductivity type to the first well; and heating the structure to drive-in the well region impurities.

Claim 15

A process for forming a self-aligned twin-well structure comprising: providing a substrate layer of predetermined conductivity type; forming a first mask structure on the substrate comprising a first silicon nitride layer and an outer photoresist layer, which structure is the complement of a first well region; depositing selected impurities in the first well region in the presence of the mask; removing the photoresist layer; depositing a relatively conformal dielectric layer on the resulting structure including the silicon nitride, a stressed dielectric layer over the silicon nitride sidewall, and the first well regions using a deposition temperature which is below the flow point of the silicon nitride; selectively removing the stressed dielectric layer on the silicon nitride sidewall; removing the silicon nitride and the overlying regions of the dielectric layer to form the dielectric into a second mask which defines a second well region self-aligned with the complement of the first well; depositing impurities in the second well in the presence of the second mask, using impurities of the opposite conductivity type to the first well; and heating the structure to drive-in the well region impurities.