Patent US4609968A successfully refreshed from Google Patents.
US4609968A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Glass inlays for use in bonding semiconductor wafers
Assignee: Meggitt Orange County Inc
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Filing: 1985-04-30
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Granted: 1986-09-02
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Expires: 2005-04-30
Abstract
Abstract A structure is provided, such as a capacitive transducer, utilizing two or more layers of semiconductor material wherein a highly insulating low capacitance bond is achieved by the invention herein between two adjacent layers by forming an inlay of glass in one layer and anodically bonding the other layer to the polished surface of the previously formed inlay.
Inventors
- 👤 Leslie B. Wilner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:07
CPC Classifications
G; G01; G01P; G01P15/00; G01P15/02; G01P15/08; G01P15/125; G01D; G01D5/00; G01D5/12; G01D5/14; G01D5/24; G01D5/241; G01D5/2417; G01P15/0802
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
168 words
A method for bonding two surfaces of the same semiconductor together, characterized by the steps of (a) selecting in a first selecting step two semiconductor surfaces to be bonded; (b) selecting in a second selecting step one of said two semiconductor surfaces from said first step; (c) etching a groove into the surface selected from said second selecting step; (d) said etching step being over said selected surface between said two surfaces selected from said first selecting step; (e) filling said groove obtained from said etching step with powdered glass; (f) fusing said powdered glass from said filling step into a solid mass; (g) polishing in a first polishing step the resulting exposed surface of said solid glass mass obtained from said fusing step to the extent necessary to obtain a desired bonding surface; (h) polishing in a second polishing step the other of said semiconductor surfaces obtained from said first selecting step; and (i) anodically bonding the polished surfaces obtained from said first and second polishing steps.
Claim 2
Independent Claim
168 words
A method for bonding two surfaces of the same semiconductor together, characterized by the steps of (a) selecting in a first selecting step two semiconductor surfaces to be bonded; (b) selecting in a second selecting step one of said two semiconductor surfaces from said first step; (c) etching a groove into the surface selected from said second selecting step; (d) said etching step being over said selected surface between said two surfaces selected from said first selecting step; (e) filling said groove obtained from said etching step with powdered glass; (f) fusing said powdered glass from said filling step into a solid mass; (g) polishing in a first polishing step the resulting exposed surface of said solid glass mass obtained from said fusing step to the extent necessary to obtain a desired bonding surface; (h) polishing in a second polishing step the other of said semiconductor surfaces obtained from said first selecting step; and (i) anodically bonding the polished surfaces obtained from said first and second polishing steps.
Claim 3
Dependent Claim
17 words
The method of claim 1, further characterized by (a) said filling step being carried out by sedimentation.
Claim 4
Dependent Claim
18 words
The method of claim 1, further characterized by (a) said filling step being carried out by silk screening.
Claim 5
Dependent Claim
26 words
The method of claim 1, further characterized by (a) said etching step being carried out only to the extent necessary to effect the desired bond width.
Claim 6
Dependent Claim
33 words
The method of claim 1, further characterized by (a) said etching step being carried out by etching said groove to a depth of within the range of between about 0.018 and 0.036 millimeters.
Claim 7
Dependent Claim
38 words
The method of claim 1, further characterized by (a) said first polishing step being carried out to the extent necessary to obtain a flat surface continuous and coplanar with said semiconductor surface obtained from said second selecting step.
Claim 8
Dependent Claim
55 words
The method of claim 1, further characterized by (a) said etching step being carried out to the extent necessary to obtain a groove larger than the extent of bond surface required for said anodically bonding step to provide a clearance on either side of said bond width for avoiding arcing during said anodically bonding step.
Claim 9
Dependent Claim
28 words
A structure comprised of at least two semiconductor wafers with the opposed surfaces of said semiconductor wafers being bonded together by the process as claimed in claim 7.
Claim 10
Dependent Claim
32 words
The method of claim 1, further characterized by (a) said fusing step being carried out at a temperature of within the range of between about 780 degrees Celsius and 1100 degrees Celsius.
Claim 11
Dependent Claim
37 words
The method of claim 1, further characterized by the additional step of (a) sawing through the bonded length obtained from said anodically bonding step to obtain at least two structures formed of two bonded together semiconductor surfaces.
Claim 12
Dependent Claim
28 words
A structure comprised of at least two semiconductor wafers with the opposed surfaces of said semiconductor wafers being bonded together by the process as claimed in claim 10.
Claim 13
Dependent Claim
42 words
The method of claim 1, further characterized by (a) prior to said etching step, coating the surface from said second selecting step with oxide; and (b) opening a pattern to be etched in the surface obtained from said coating step by photolithography.
Claim 14
Dependent Claim
28 words
A structure comprised of at least two semiconductor wafers with the opposed surfaces of said semiconductor wafers being bonded together by the process as claimed in claim 12.
Claim 15
Dependent Claim
43 words
The method of claim 1, further characterized by (a) prior to said etching step, coating the surface from said second selecting step with oxide; and (b) opening a pattern to be etched in the surface obtained from said coating step by abrasive sawing.
Claim 16
Dependent Claim
28 words
A structure comprised of at least two semiconductor wafers with the opposed surfaces of said semiconductor wafers being bonded together by the process as claimed in claim 1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-01 | 1990-03-03 | 1990-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-01 | 1994-03-03 | 1994-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-01 | 1998-03-03 | 1998-09-02 | $7700.00 | Window Closed / Lapsed |