Minimal logic synchronous up/down counter implementations for CMOS

Claim 2

An up/down (U/D) counter for counting a toggle-in signal, said counter having two or more stages, each stage comprising: a clock flip-flop having a data input and Q and Q outputs providing a counter stage output at one of said outputs; a feedback circuit including an exclusive-OR gate having an input coupled to an output of said flip-flop and a second input adapted to receive a toggle-in signal and an output signal coupled to said data input of said flip-flop; and a multiplexer having a first input coupled to said Q output of said flip-flop and a second input coupled to said Q output of said flip-flop and a single switch control input which, depending upon the binary state of an applied up/down count control signal, selectively connects either said first input or said second input to a multiplexer output port providing toggle out data for input to another of said counter stages.

Claim 3

An up/down (U/D) counter according to claim 1 wherein said flip-flop, feedback path and multiplexer are integrated in a CMOS integrated circuit.

Claim 4

An up/down (U/D) counter according to claim 1 wherein said flip-flop, feedback path and multiplexer are integrated in a CMOS integrated circuit.

Claim 5

An up/down (U/D) counter stage, comprising: an exclusive-OR logic gate having a first input for receiving a toggle-in signal to be counted, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to a clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; a multiplexer having an U/D input for receiving an U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of said multiplexer and a second input coupled to also receive said toggle-in signal and having an output providing a toggle-out signal serving as the toggle-in signal for another U/D counter stage.

Claim 6

An up/down (U/D) counter stage, comprising: an exclusive-OR logic gate having a first input for receiving a toggle-in signal to be counted, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to a clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; a multiplexer having an U/D input for receiving an U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of said multiplexer and a second input coupled to also receive said toggle-in signal and having an output providing a toggle-out signal serving as the toggle-in signal for another U/D counter stage.

Claim 7

A counter according to claim 4 wherein said OR gate, flip-flop, multiplexer and AND gate are integrated in a CMOS integrated circuit.

Claim 8

An up/down (U/D) counter, comprising N counter stages coupled in cascade, each stage adapted to receive a common external U/D control signal and a common clock signal, a first stage of the cascade receiving a toggle-in signal and each of the first N-1 stages providing a toggle-out signal serving as a toggle-in signal to the next stage of the cascade, each stage providing an output, each stage comprising: an exclusive OR logic gate having a first input for receiving said external toggle-in signal, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive OR gate, a clock input for connection to said clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive OR gate and providing an output of said counter stage; a multiplexer having an U/D input for receiving said external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of said multiplexer and a second input coupled to also receive said toggle-in signal and having an output providing said toggle-out signal serving as the toggle-in signal for a subsequent cascaded U/D counter stage.

Claim 9

An up/down (U/D) counter, comprising N counter stages coupled in cascade, each stage adapted to receive a common external U/D control signal and a common clock signal, a first stage of the cascade receiving a toggle-in signal and each of the first N-1 stages providing a toggle-out signal serving as a toggle-in signal to the next stage of the cascade, each stage providing an output, each stage comprising: an exclusive OR logic gate having a first input for receiving said external toggle-in signal, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive OR gate, a clock input for connection to said clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive OR gate and providing an output of said counter stage; a multiplexer having an U/D input for receiving said external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of said multiplexer and a second input coupled to also receive said toggle-in signal and having an output providing said toggle-out signal serving as the toggle-in signal for a subsequent cascaded U/D counter stage.

Claim 10

A counter according to claim 6 wherein all stages of said counter are integrated in a CMOS integrated circuit.

Claim 11

An N-stage up/down (U/D) counter, comprising: a first counter stage including: an exclusive OR logic gate having a first input for receiving an external toggle-in signal, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to an external clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; and a multiplexer having an U/D input for receiving an external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and N-1 further counter stages, cascaded with said first stage, each of said further stages including: an AND gate having a first input coupled to said toggle-in signal and additional inputs coupled to respective outputs of the multiplexers of each previous counter stage of said cascade, and an output; an exclusive OR logic gate having a first input coupled to said output of said AND gate, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to an external clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; and a multiplexer having an U/D input for receiving an external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of the multiplexer of each stage and a second input coupled to said toggle-in signal and having an output providing a toggle-out signal for another U/D counter.

Claim 12

An N-stage up/down (U/D) counter, comprising: a first counter stage including: an exclusive OR logic gate having a first input for receiving an external toggle-in signal, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to an external clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; and a multiplexer having an U/D input for receiving an external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and N-1 further counter stages, cascaded with said first stage, each of said further stages including: an AND gate having a first input coupled to said toggle-in signal and additional inputs coupled to respective outputs of the multiplexers of each previous counter stage of said cascade, and an output; an exclusive OR logic gate having a first input coupled to said output of said AND gate, a second input and an output; a flip-flop having a data input coupled to the output of said exclusive-OR gate, a clock input for connection to an external clock signal, and Q and Q outputs, the Q output being coupled to the second input of said exclusive-OR gate and providing an output of said counter stage; and a multiplexer having an U/D input for receiving an external U/D signal for controlling whether the stage counts up or down, a first data input coupled to the Q output of said flip-flop, a second input coupled to the Q output of said flip-flop and an output; and an AND gate having a first input coupled to said output of the multiplexer of each stage and a second input coupled to said toggle-in signal and having an output providing a toggle-out signal for another U/D counter.

Claim 13

A counter according to claim 8 wherein said N-stages are integrated in a CMOS integrated circuit.