Patent US4621337A successfully refreshed from Google Patents.
US4621337A
Expired / Lapsed
US
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Transformation circuit for implementing a collapsed Walsh-Hadamard transform
Assignee: Eastman Kodak Co
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Filing: 1983-08-11
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Granted: 1986-11-04
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Expires: 2003-08-11
Abstract
Abstract A unit transformation circuit transforms three discrete input signals into a set of transform coefficient signals characteristic of a "collapsed" Walsh-Hadamard transform. The unit transformation circuit includes two tiers of arithmetic networks. In the first tier, a pair of arithmetic networks generates (A) first sum and difference signals from the first and second input signals and (B) second sum and difference signals from the second and third input signals. Arithmetic networks in the second tier generate a set of coefficient signals from (A) the sum of the first and second sum signals (B) the sum of the first and second difference signals and (C) the difference between the first and second difference signals. The unit transformation circuit forms a fundamental circuit element from which more complex circuits are constructed capable of transforming larger numbers of discrete input signals.
Inventors
- 👤 Billy E. Cates
- 👤 Ronald S. Cok
- 👤 Bryce E. Bayer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:48
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/145
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A unit transformation circuit for transforming three discrete input signals into a set of transform coefficient signals, said circuit comprising: means for generating a first sum signal and a first difference signal from the first and second discrete input signals; means for generating a second sum signal and a second difference signal from the second and third discrete input signals; and means for generating a set of transform coefficient signals from (A) the sum of said first and second sum signals, (B) the sum of said first and second difference signals, and (C) the difference between said first and second difference signals.
Claim 2
Dependent Claim
102 words
A unit transformation circuit for transforming three discrete input signals into a set of transform coefficient signals, said circuit comprising: means for generating a first sum signal and a first difference signal from the first and second discrete input signals; means for generating a second sum signal and a second difference signal from the second and third discrete input signals; and means for generating a set of transform coefficient signals from (A) the sum of said first and second sum signals, (B) the sum of said first and second difference signals, and (C) the difference between said first and second difference signals.
Claim 3
Dependent Claim
76 words
A unit transformation circuit according to claim 1 in which said means for generating a set of transform coefficient signals comprises: means for generating a first transform coefficient signal from the sum of said first and second sum signals; means for generating a second transform coefficient signal from the sum of said first and second difference signals; and means for generating a third transform coefficient signal from the difference between said first and second difference signals.
Claim 4
Dependent Claim
36 words
A unit transformation circuit according to claim 2 in which the set of transform coefficient signals includes a fourth transform coefficient signal that is obtained by means providing a duplicate of said second transform coefficient signal.
Claim 5
Dependent Claim
32 words
A transformation circuit comprising at least N unit transformation circuits each according to claim 1 and in which 3N discrete input signals are transformed into a corresponding set of transform coefficient signals.
Claim 6
Dependent Claim
51 words
An inverse transformation circuit for inverse transforming a set of transform coefficient signals into a set of processed discrete signals, the inverse transformation circuit comprising a plurality of unit transformation circuits each according to claim 1 in which the set of transform coefficient signals are inverse transformed into processed discrete signals.
Claim 7
Dependent Claim
194 words
A transformation circuit including at least one unit transformation circuit for transforming discrete signals provided at a predetermined period P, each unit transformation circuit comprising, a first input terminal for receiving a first discrete signal to be transformed; a second input terminal for receiving a second discrete signal displaced by predetermined period P with respect to said first discrete signal; a third input terminal for receiving a third discrete signal displaced by predetermined period P with respect to said second discrete signal; first arithmetic network means connected to said first and second input terminals for providing a first sum and a first difference signal; second arithmetic network means connected to said second and third input terminals for providing a second sum and a second difference signal; third arithmetic network means for receiving said first and second sum signals and for providing a third sum signal; and fourth arithmetic network means for receiving said first and second difference signals and for providing a fourth sum signal and a third difference signal, whereby the third difference signal and the third and fourth sum signals represent a transformation of the discrete signals provided to said input terminals.
Claim 8
Dependent Claim
194 words
A transformation circuit including at least one unit transformation circuit for transforming discrete signals provided at a predetermined period P, each unit transformation circuit comprising, a first input terminal for receiving a first discrete signal to be transformed; a second input terminal for receiving a second discrete signal displaced by predetermined period P with respect to said first discrete signal; a third input terminal for receiving a third discrete signal displaced by predetermined period P with respect to said second discrete signal; first arithmetic network means connected to said first and second input terminals for providing a first sum and a first difference signal; second arithmetic network means connected to said second and third input terminals for providing a second sum and a second difference signal; third arithmetic network means for receiving said first and second sum signals and for providing a third sum signal; and fourth arithmetic network means for receiving said first and second difference signals and for providing a fourth sum signal and a third difference signal, whereby the third difference signal and the third and fourth sum signals represent a transformation of the discrete signals provided to said input terminals.
Claim 9
Dependent Claim
164 words
A transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period P, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed; first delay means connected to said input terminal and having a delay period of P; second delay means connected to said first delay means and having a delay period of P; first arithmetic network means connected to the output of said first delay means and to said input terminal for providing a first sum and a first difference signal; second arithmetic network means connected to the outputs of said first and second delay means for providing a second sum and a second difference signal; third arithmetic network means for receiving said first and second sum signals and for providing a third sum signal; and fourth arithmetic network means for receiving said first and second difference signals and for providing a fourth sum signal and a third difference signal.
Claim 10
Dependent Claim
164 words
A transformation circuit including at least one unit transformation circuit for transforming discrete signals occurring at a predetermined period P, each unit transformation circuit comprising an input terminal for receiving the discrete signals to be transformed; first delay means connected to said input terminal and having a delay period of P; second delay means connected to said first delay means and having a delay period of P; first arithmetic network means connected to the output of said first delay means and to said input terminal for providing a first sum and a first difference signal; second arithmetic network means connected to the outputs of said first and second delay means for providing a second sum and a second difference signal; third arithmetic network means for receiving said first and second sum signals and for providing a third sum signal; and fourth arithmetic network means for receiving said first and second difference signals and for providing a fourth sum signal and a third difference signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-03 | 1990-05-05 | 1990-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-03 | 1994-05-05 | 1994-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-03 | 1998-05-05 | 1998-11-04 | $7700.00 | Window Closed / Lapsed |