Decoupling capacitor for Pin Grid Array package

Claim 2

A decoupling capacitor for use with a pin grid array package, the pin grid array package having an array of pins extending from one side of a substrate, the center of the one side having no pins extending therefrom and defining a chip cavity area, at least some of the pins surrounding the chip cavity area being power and ground pins, the capacitor including: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a ground conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a power conductor; a plurality of first leads in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in electrical contact with said second conductor and extending outwardly therefrom; the power or ground configuration of said first and second leads corresponding to the power or ground configuration of said pin grid array pins; an insulating material encapsulating said dielectric body and conductors, said leads extending through said insulating material; and said encapsulated assembly being dimensioned to fit within said center of said pin grid array package.

Claim 3

The capacitor of claim 1 wherein: said encapsulated assembly is substantially rectangular.

Claim 4

The capacitor of claim 2 wherein: said encapsulated assembly is substantially square.

Claim 5

The capacitor of claim 1 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 6

The capacitor of claim 1 wherein: each of said leads comprise a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 7

The capacitor of claim 1 including: stand off means provided on said encapsulating material of said decoupling capacitor.

Claim 8

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side of a substrate, the center of said one side having no pins extending therefrom and defining a chip cavity area, at least some of the pins surrounding the chip cavity area being power and ground pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capacitor means, said decoupling capacitor means being positioned in the center of said pin grid array package and thus being interposed between said chip cavity area of said pin grid array package and said circuit board, said capacitor means comprising: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a ground conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a power conductor; a plurality of first leads in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in electrical contact with said second conductor and extending outwardly therefrom; the power or ground configuration of said first and second leads corresponding to the power or ground configuration of said in grid array pins; an insulating material encapsulating said dielectric body and conductors, said leads extending through said insulating material; and said encapsulated assembly being dimensioned to fit within said center of said pin grid array package.

Claim 9

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side of a substrate, the center of said one side having no pins extending therefrom and defining a chip cavity area, at least some of the pins surrounding the chip cavity area being power and ground pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capacitor means, said decoupling capacitor means being positioned in the center of said pin grid array package and thus being interposed between said chip cavity area of said pin grid array package and said circuit board, said capacitor means comprising: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a ground conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a power conductor; a plurality of first leads in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in electrical contact with said second conductor and extending outwardly therefrom; the power or ground configuration of said first and second leads corresponding to the power or ground configuration of said in grid array pins; an insulating material encapsulating said dielectric body and conductors, said leads extending through said insulating material; and said encapsulated assembly being dimensioned to fit within said center of said pin grid array package.

Claim 10

The subassembly of claim 7 wherein: said encapsulated assembly is substantially rectangular.

Claim 11

The subassembly of claim 8 wherein: said encapsulated assembly is substantially square.

Claim 12

The subassembly of claim 7 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 13

The subassembly of claim 7 wherein: each of said leads comprise a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 14

The subassembly of claim 7 wherein: stand off means provided on said insulating material of said decoupling capacitor.

Claim 15

The subassembly of claim 12 wherein: said stand off means define a space between said decoupling capacitor and said circuit board.

Claim 16

The subassembly of claim 7 including: second spaced holes in said circuit board for receiving said power and ground leads of said decoupling capacitor.

Claim 17

The subassembly of claim 7 wherein: said power and ground leads of said decoupling capacitor are in the same holes as the corresponding power and ground pins of said pin grid array.

Claim 18

A decoupling capacitor for use with a pin grid array package, the pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins, the capacitor including: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of the pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 19

A decoupling capacitor for use with a pin grid array package, the pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins, the capacitor including: a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of the pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 20

The capacitor of claim 16 wherein: said insulated assembly is substantially rectangular.

Claim 21

The capacitor of claim 17 wherein: said insulated assembly is substantially square.

Claim 22

The capacitor of claim 16 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 23

The capacitor of claim 16 wherein: each of said leads comprises a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 24

The capacitor of claim 16 including: stand off means provided on said insulated assembly.

Claim 25

The capacitor of claim 16 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 26

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capacitor means, said decoupling capacitor means being alinged with said central pin free area of said pin grid array package and electrically communicating with said circuit board, said capacitor means comprising; a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of the pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 27

An electronic subassembly comprising: a pin grid array package, said pin grid array package having an array of pins extending from one side thereof and surrounding a central pin free area of predetermined size, at least some of the pins surrounding the central pin free area being first and second voltage level pins; a circuit board, said circuit board having first spaced holes receiving said pin grid array package pins; and decoupling capacitor means, said decoupling capacitor means being alinged with said central pin free area of said pin grid array package and electrically communicating with said circuit board, said capacitor means comprising; a flat dielectric body having a pair of opposed surfaces; a first conductor on one of said opposed surfaces of said dielectric body defining a first voltage level conductor; a second conductor on the other of the said opposed surfaces of said dielectric body defining a second voltage level conductor; a plurality of first leads in a predetermined configuration in electrical contact with said first conductor and extending outwardly therefrom; a plurality of second leads in a predetermined configuration in electrical contact with said second conductor and extending outwardly therefrom; the configurations of said first and second leads corresponding to configurations of first and second voltage levels of pins of the pin grid array package; an insulating material surrounding said dielectric body and conductors, said first and second leads extending through said insulating material; and said dielectric body, first conductor, second conductor and insulating material defining an insulated assembly, the size of said insulated assembly being less than the size of the central pin free area.

Claim 28

The subassembly of claim 23 wherein: said decoupling capacitor means is interposed between said central pin free area of said pin grid array package and said circuit board.

Claim 29

The subassembly of claim 23 wherein: said insulated assembly is substantially rectangular.

Claim 30

The subassembly of claim 25 wherein: said insulated assembly is substantially square.

Claim 31

The subassembly of claim 23 wherein: said leads extend outwardly and downwardly perpendicular to said conductors.

Claim 32

The subassembly of claim 23 wherein: each of said leads comprises a tab having an opening therethrough for receiving one of said pins from said pin grid array package.

Claim 33

The subassembly of claim 23 including: stand off means provided on said insulated assembly.

Claim 34

The subassembly of claim 29 wherein: said standoff means defines a space between said decoupling capacitor and said circuit board.

Claim 35

The subassembly of claim 23 including: second spaced holes in said circuit board for receiving said first and second voltage level leads of said decoupling capacitor.

Claim 36

The subassembly of claim 31 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 37

The subassembly of claim 23 wherein: said dielectric body, first conductor, second conductor, first leads, second leads and insulating material have a size which is less than the size of the central pin free area.

Claim 38

The subassembly of claim 23 wherein: said first and second voltage level leads of said decoupling capacitor are received in the same holes as the corresponding first and second voltage level pins of said pin grid array package.