Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
184 words
A read-only memory comprising memory cells each having a vertical metal oxide semiconductor field effect transistor and a bit line, said vertical metal oxide semiconductor field effect transistor having a gate electrode serving as a word line, a source and a drain, said source and said drain being constituted by first and second diffusion layers, and a vertical channel region between said source and said drain, said gate electrode being formed on a side wall of a trench, said trench havig side wall surfaces substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and a interconnecting bottom surface substantially perpendicular to said side wall surfaces, said first and second diffusion layers being of a second conductivity type formed in an upper portion of said semiconductor substrate and in a bottom of said trench, respectively, said bit lines being formed in a predetermined pattern, one of said first and second diffusion layers being connected to said bit line through a contact hole and the other of said first and second diffusion layers being used as a common current line.
Claim 2
Dependent Claim
184 words
A read-only memory comprising memory cells each having a vertical metal oxide semiconductor field effect transistor and a bit line, said vertical metal oxide semiconductor field effect transistor having a gate electrode serving as a word line, a source and a drain, said source and said drain being constituted by first and second diffusion layers, and a vertical channel region between said source and said drain, said gate electrode being formed on a side wall of a trench, said trench havig side wall surfaces substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and a interconnecting bottom surface substantially perpendicular to said side wall surfaces, said first and second diffusion layers being of a second conductivity type formed in an upper portion of said semiconductor substrate and in a bottom of said trench, respectively, said bit lines being formed in a predetermined pattern, one of said first and second diffusion layers being connected to said bit line through a contact hole and the other of said first and second diffusion layers being used as a common current line.
Claim 3
Dependent Claim
23 words
A memory according to claim 1, wherein said contact hole is formed in accordance with date to be written into a given cell.
Claim 4
Dependent Claim
16 words
A memory according to claim 1, wherein said vertical channel region comprises a channel doped region.
Claim 5
Dependent Claim
37 words
A memory according to claim 1, wherein said trench comprises a grid-like trench, a memory cell is in a region surrounded by said grid-like trench, and said second diffusion layer being used as said common current line.
Claim 6
Dependent Claim
61 words
A memory according to claim 4, wherein said trench has a pattern narrowed in a direction parallel to the bit line and widened in a direction parallel to the word line, a narrowed pattern portion of said trench is filled by said gate electrode, and a widened pattern portion of said trench is filled by said gate electrode and other material.
Claim 7
Dependent Claim
24 words
A memory according to claim 1, wherein said trench comprises an island-like trench, and a memory cell region is located in said island-like trench.
Claim 8
Dependent Claim
46 words
A memory according to claim 6, wherein a distance between adjacent trenches has a pattern narrowed along a direction parallel to the bit line and widened along a direction parallel to the word line, and said first diffusion layer being used as said common current line.
Claim 9
Dependent Claim
29 words
A memory according to claim 1, wherein said vertical channel region comprises a channel doped region whoe impurity concentration corresponds to data to be written into a given cell.
Claim 10
Dependent Claim
26 words
A memory according to claim 8, wherein said channel doped region has an impurity concentration corresponding to the data to be written into a given cell.