Data processing system having no bus utilization priority control

Claim 1

A data processing system having no bus utilization priority control, comprising: an instruction processing unit operating in accordance with a plurality of first microinstructions prestored therein; an execution unit which operates in accordance with a plurality of second microinstructions prestored therein and which operates synchronously with said instruction processing unit; and a bus operatively connected with said instruction processing unit and said execution unit; said execution unit generating a pause command when said execution unit uses said bus during the next microinstruction cycle of said second microinstructions; said instruction processing unit being supplied with said pause command, and including a circuit which causes double occurrences of one of said first microinstructions in response to said pause command in the event that said instruction processing unit uses said bus during the next microinstruction cycle of said second microinstructions, said instruction processing unit further including an instruction processing portion which is arranged to temporarily disable the first microinstruction of said double occurrences in response to said pause command; said instruction processing unit comprising: a first control memory for previously storing said first microinstructions, a first control memory address generator for generating address signals for deriving microinstructions from said first microinstructions within said first control memory, a first address register, a multiplexer for selectively allowing either said first control memory address generator or said first address register to couple with said first control memory, said multiplexer normally coupling said first control memory address generator with said first control memory, said first address register receiving the output of said multiplexer and updating the content thereof, a first microinstruction register for storing each microinstruction derived from said first control memory, said first microinstruction register communicating the content thereof back to said first control memory address generator, and a controller receiving the content of said first microinstruction register, said controller, in response to said pause command, allowing said multiplexer to couple said first address register with said first control memory in order to cause said double occurrences of said first microinstructions and at the same time disabling said insturction processing portion in case said instruction processing unit uses said bus during the next microinstruction cycle of said processing unit.