Back biased CMOS device with means for eliminating latchup

Claim 2

A four layer CMOS integrated circuit semiconductor device comprising: a semiconductor substrate having a p-type conductivity; an integrated circuit formed in a surface area of said substrate, said circuit having elements including a plurality of n-well regions, n+ and p+ diffusions in said n-well regions and other n+ and p+ diffusions outside of said n-well regions, means interconnecting said diffusions in a predetermined manner and integral lead means forming a network connecting said n-well regions to a V CC power supply; means among said circuit elements forming an output buffer and connected to an output terminal of said device adapted for connection with an external electrical circuit that normally draws current during the powerup mode for said device; means in said substrate forming a guardring surrounding said integrated circuit elements; means in said substrate forming a backbias generator for producing a backbias voltage to said substrate; latchup prevention means in said substrate located outside of and spaced from said guardring comprising an integrated sub-circuit including n+ and p+ diffusions within an n-well region and connected to said V CC power supply network for said integrated circuit, said latchup prevention means being operative to limit the forward biasing of parasitic transistors inherently formed within said four layer integrated circuit during the powerup phase of said device.

Claim 3

The CMOS integrated circuit device of claim 1 wherein said means for preventing latchup during the powerup phase is a clamp diode located outside of said guardring and connected electrically to said n-well regions of said circuit by said V CC network.

Claim 4

The CMOS integrated circuit device of claim 2 wherein said clamp diode is comprised of a plurality of elongated n+ and p+ diffusions within an n-well region in said substrate.

Claim 5

The CMOS integrated circuit device of claim 2 wherein said clamp diode has a relatively low forward resistance of not more than 4 ohms.

Claim 6

The CMOS integrated circuit device of claim 2 wherein said clamp diode has an overall length that is at least 30 times its width.

Claim 7

The CMOS integrated circuit device of claim 2 including a p+ protective diffusion surrounding said clamp diode.

Claim 8

The CMOS integrated circuit device of claim 1 wherein said means for preventing latchup of the CMOS circuit in the powerup mode is a junction field effect transistor.

Claim 9

The CMOS integrated circuit device of claim 7 wherein said junction field effect transistor comprises a central p+ diffusion connected to ground potential (V SS ) a continuous n-well region spaced from and surrounding said p+ diffusion and an n+ diffusion connected to the device power supply (V CC ) within said n-well region, said n-well region and its included n+ diffusion being close enough to said p+ diffusion so that when power is applied, the n-well depletion region will expand to close off any conductive path from said p+ diffusion to the substrate below said junction field effect transistor.

Claim 10

The CMOS integrated circuit device of claim 8 wherein said p+ diffusion is essentially square shaped with a side dimension of around 4 microns and said n-well region is spaced about 4 microns from the sides of said p+ diffusion.

Claim 11

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a well region having a second conductivity type in the surface area of said semiconductor substrate; first and second semiconductor regions of the first conductivity type formed in the surface area of said substrate; third and fourth semiconductor regions of a second conductivity type formed in the surface area of said substrate; a first gate electrode insulatively formed on a surface area of said substrate which lies between said first and second semiconductor regions to form a first transistor; a second gate electrode insulatively arranged on the surface area of said well region which lies between said third and fourth semiconductor regions to form a second transistor; means for interconnecting said first and second transistors to form a complementary metal oxide semiconductor element; voltage generator means on said device for applying a reverse bias voltage to said substrate; means forming a guardring in the surface of said substrate surrounding said first and second transistors; and sub-circuit means of additional semiconductor regions forming a clamp diode in the surface of said substrate outside of said guardring said sub-circuit means and said well region being connected to a conductive network between an external power source for said device and ground potential to limit the forward biasing of parasitic transistors formed in the device and thereby prevent latchup of the device in its powerup mode.

Claim 12

A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a well region having a second conductivity type in the surface area of said semiconductor substrate; first and second semiconductor regions of the first conductivity type formed in the surface area of said substrate; third and fourth semiconductor regions of a second conductivity type formed in the surface area of said substrate; a first gate electrode insulatively formed on a surface area of said substrate which lies between said first and second semiconductor regions to form a first transistor; a second gate electrode insulatively arranged on the surface area of said well region which lies between said third and fourth semiconductor regions to form a second transistor; means for interconnecting said first and second transistors to form a complementary metal oxide semiconductor element; voltage generator means on said device for applying a reverse bias voltage to said substrate; means forming a guardring in the surface of said substrate surrounding said first and second transistors; and sub-circuit means of additional semiconductor regions forming a clamp diode in the surface of said substrate outside of said guardring said sub-circuit means and said well region being connected to a conductive network between an external power source for said device and ground potential to limit the forward biasing of parasitic transistors formed in the device and thereby prevent latchup of the device in its powerup mode.