Video camera iris control circuit

Claim 2

An iris control circuit for a video camera, comprising; drive coil means including a drive coil for driving the iris of a video camera; means for inputting an iris control signal to said drive coil means; detecting circuit means for detecting a counterelectromotive force produced in said drive coil; feedback circuit means for generating a feedback signal in response to an output of said detecting circuit means, said feedback signal being applied to said drive coil means; said drive coil means further comprising means for controlling the flow of current through said drive coil in response to at least one of said iris control signal and said feedback signal.

Claim 3

The iris control circuit of claim 1, wherein said detecting circuit means comprises a voltage divider circuit having a first end terminal connected to a first terminal of said drive coil and a second end terminal connected to a reference terminal.

Claim 4

The iris control circuit of claim 1, said drive coil means comprising an operational amplifier for supplying drive current to said drive coil in response to both said iris control signal and said feedback signal.

Claim 5

The iris control circuit of claim 3, wherein said feedback circuit means comprises a variable resistor for variably adjusting a feedback ratio of said iris control circuit.

Claim 6

The iris control circuit of claim 4, wherein said detecting circuit means further comprises a second operational amplifier having inputs respectively coupled to said voltage divider circuit and to a second terminal of said drive coil, and an output coupled through said variable resistor to an input of said first-mentioned operational amplifier.

Claim 7

An iris control circuit for a video camera comprising: a first operational amplifier, first and second resistors, and a reference voltage source, an inverting input terminal of said first operational amplifier being coupled through said first resistor and said reference voltage source to a ground terminal, and a noninverting input of said first operational amplifier being coupled through said second resistor to a source of an iris control signal; a drive coil for driving the iris of said video camera and a third resistor, said third resistor having one terminal coupled to said ground terminal and a second terminal coupled through said drive coil to an output of said first operational amplifier; fourth and fifth resistors connected in series with one another, the series connection of said fourth and fifth resistors having one end terminal coupled to said ground terminal and the other end terminal coupled to said output of said first operational amplifier; a second operational amplifier and sixth through eighth resistors, an inverting input terminal of said second operational amplifier being coupled through said sixth resistor to a connection point of said fourth and fifth resistors, a noninverting input terminal of said second operational amplifier being coupled through said seventh resistor to a connection point of said drive coil and said third resistor, and said eighth resistor being coupled between said noninverting input terminal of said second operational amplifier and said ground terminal; and a variable resistor coupled between an output of said second operational amplifier and said noninverting input terminal of said first operational amplifier.

Claim 8

An iris control circuit for a video camera comprising: a first operational amplifier, first and second resistors, and a reference voltage source, an inverting input terminal of said first operational amplifier being coupled through said first resistor and said reference voltage source to a ground terminal, and a noninverting input of said first operational amplifier being coupled through said second resistor to a source of an iris control signal; a drive coil for driving the iris of said video camera and a third resistor, said third resistor having one terminal coupled to said ground terminal and a second terminal coupled through said drive coil to an output of said first operational amplifier; fourth and fifth resistors connected in series with one another, the series connection of said fourth and fifth resistors having one end terminal coupled to said ground terminal and the other end terminal coupled to said output of said first operational amplifier; a second operational amplifier and sixth through eighth resistors, an inverting input terminal of said second operational amplifier being coupled through said sixth resistor to a connection point of said fourth and fifth resistors, a noninverting input terminal of said second operational amplifier being coupled through said seventh resistor to a connection point of said drive coil and said third resistor, and said eighth resistor being coupled between said noninverting input terminal of said second operational amplifier and said ground terminal; and a variable resistor coupled between an output of said second operational amplifier and said noninverting input terminal of said first operational amplifier.

Claim 9

The iris control circuit of claim 6, further comprising a ninth resistor coupled between said output of said first operational amplifier and said inverting input terminal of said first operational amplifier, and a tenth resistor coupled between said output of said second operational amplifier and said inverting input terminal of said second operational amplifier.

Claim 10

An iris control circuit for a video camera, comprising: a first resistor, a first terminal of said first resistor being coupled to a source of an iris control signal; a first switch having a first terminal coupled to a second terminal of said first resistor; a capacitor coupled between a second terminal of said first switch and a ground terminal; a field effect transistor having a gate coupled to said second terminal of said first switch and a drain connected to a power source terminal; a second resistor coupled between a source of said field effect transistor and said ground terminal; a first operational amplifier; a third resistor coupled between said source of said field effect transistor and a noninverting input terminal of said first operational amplifier; a fourth resistor and a reference voltage source, an inverting input terminal of said first operational amplifier being coupled through said fourth resistor and said reference voltage source to said ground terminal; a drive coil and a fifth resistor, a first terminal of said drive coil being coupled to an output of said first operational amplifier, and a second terminal of said drive coil being coupled through said fifth resistor to said ground terminal; a voltage divider circuit comprising sixth and seventh resistors coupled in series between said output of said first operational amplifier and said ground terminal; a second operational amplifier and eighth through tenth resistors, an inverting input terminal of said second operational amplifier being coupled through said eighth resistor to a connection point of said sixth and seventh resistors, a noninverting input terminal of said second operational amplifier being coupled through said ninth resistor to a connection point of said drive coil and said fifth resistor and through said tenth resistor to said ground terminal; an eleventh resistor having a first terminal coupled to an output of said second operational amplifier; a twelfth resistor having a first terminal coupled to a second terminal of said eleventh resistor and a second terminal coupled to said noninverting input terminal of said first operational amplifier; and a second switch coupled in parallel with said twelfth resistor, said first and second switches being ganged together.

Claim 11

An iris control circuit for a video camera, comprising: a first resistor, a first terminal of said first resistor being coupled to a source of an iris control signal; a first switch having a first terminal coupled to a second terminal of said first resistor; a capacitor coupled between a second terminal of said first switch and a ground terminal; a field effect transistor having a gate coupled to said second terminal of said first switch and a drain connected to a power source terminal; a second resistor coupled between a source of said field effect transistor and said ground terminal; a first operational amplifier; a third resistor coupled between said source of said field effect transistor and a noninverting input terminal of said first operational amplifier; a fourth resistor and a reference voltage source, an inverting input terminal of said first operational amplifier being coupled through said fourth resistor and said reference voltage source to said ground terminal; a drive coil and a fifth resistor, a first terminal of said drive coil being coupled to an output of said first operational amplifier, and a second terminal of said drive coil being coupled through said fifth resistor to said ground terminal; a voltage divider circuit comprising sixth and seventh resistors coupled in series between said output of said first operational amplifier and said ground terminal; a second operational amplifier and eighth through tenth resistors, an inverting input terminal of said second operational amplifier being coupled through said eighth resistor to a connection point of said sixth and seventh resistors, a noninverting input terminal of said second operational amplifier being coupled through said ninth resistor to a connection point of said drive coil and said fifth resistor and through said tenth resistor to said ground terminal; an eleventh resistor having a first terminal coupled to an output of said second operational amplifier; a twelfth resistor having a first terminal coupled to a second terminal of said eleventh resistor and a second terminal coupled to said noninverting input terminal of said first operational amplifier; and a second switch coupled in parallel with said twelfth resistor, said first and second switches being ganged together.

Claim 12

The video camera iris control circuit of claim 8, further comprising a thirteenth resistor coupled between said output of said first operational amplifier and said inverting input terminal of said first operational amplifier, and a fourteenth resistor coupled between said output of said second operational amplifier and said inverting input terminal of said second operational amplifier.