Address decoder circuit

Claim 2

An address decoder circuit for forming word line selection signals by applying thereto an m-bit address signal, said decoder circuit comprising a first enhancement-type MOS transistor, its gate serving to receive a decoder output from an i-bit address signal (i being smaller than m), its source serving to receive a decoder output from an (m-i)-bit address signal, and its drain being connected to a word line of a memory cell array, an inverter for inverting said decoder output from an i-bit address, and a second enhancement-type MOS transistor, its gate serving to receive the output from said inverter, its drain being connected to said word line and its source being connected to a power source terminal.

Claim 3

The address decoder circuit of claim 1 further comprising a capacitor between the gate and the drain of said first enhancement-type MOS transistor and a depletion-type MOS transistor, the source thereof being connected to the source of said first enhancement-type MOS transistor, the drain thereof being connected to the drain of said first enhancement-type MOS transistor, and the gate thereof being connected in common with the gate of said first enhancement-type MOS transistor.

Claim 4

The address decoder circuit of claim 1 wherein said decoder output from an i-bit address signal is applied through a third enhancement-type MOS transistor to the gate of said first enhancement-type MOS transistor.

Claim 5

An address decoder circuit for forming word line selection signals by receiving thereto an m-bit address signal, said decoder circuit comprising a first decoder circuit serving to receive an i-bit address signal (i being smaller than m) and to output 2 i first decoder output signals, a second decoder circuit serving to receive an (m-i)-bit address signal and to output 2 m-i second decoder output signals, and 2 i word line driving circuits each serving to receive one of said first decoder output signals and said 2 m-i second decoder output signals and to output 2 m-i word line driving signals through 2 m-i word lines which are each connected to a plurality of memory cells, each of said word line driving circuits comprising an inverter for inverting one of said first decoder output signals, and a plurality of unit circuits each including a first enhancement-type MOS transistor of which the gate serves to receive said one of said first decoder output signals, the source serves to receive one of said second decoder output signals and the drain is connected to one of said 2 m-i word lines, and a second enhancement-type MOS transistor of which the gate serves to receive the output from said inverter, the drain is connected to said one of said 2 m-i word lines and the source is connected to a power source terminal.

Claim 6

An address decoder circuit for forming word line selection signals by receiving thereto an m-bit address signal, said decoder circuit comprising a first decoder circuit serving to receive an i-bit address signal (i being smaller than m) and to output 2 i first decoder output signals, a second decoder circuit serving to receive an (m-i)-bit address signal and to output 2 m-i second decoder output signals, and 2 i word line driving circuits each serving to receive one of said first decoder output signals and said 2 m-i second decoder output signals and to output 2 m-i word line driving signals through 2 m-i word lines which are each connected to a plurality of memory cells, each of said word line driving circuits comprising an inverter for inverting one of said first decoder output signals, and a plurality of unit circuits each including a first enhancement-type MOS transistor of which the gate serves to receive said one of said first decoder output signals, the source serves to receive one of said second decoder output signals and the drain is connected to one of said 2 m-i word lines, and a second enhancement-type MOS transistor of which the gate serves to receive the output from said inverter, the drain is connected to said one of said 2 m-i word lines and the source is connected to a power source terminal.

Claim 7

The address decoder circuit of claim 4 wherein each of said unit circuits further includes a capacitor between the gate and the drain of said first enhancement-type MOS transistor, and a depletion-type MOS transistor, the source thereof being connected to the source of said first enhancement-type transistor, the drain thereof being connected to the drain of said first enhancement-type MOS transistor, and the gate thereof being connected in common with the gate of said first enhancement-type MOS transistor.

Claim 8

The address decoder circuit of claim 4 wherein each of said word line driving circuits further comprises one or more third enhancement-type MOS transistors through which said one of said first decoder output signals is inputted to the gates of said first enhancement-type MOS transistors.

Claim 9

The address decoder circuit of claim 2 wherein a decoder output is received through a third enhancement-type MOS transistor to the gate of said first enhancement-type MOS transistor.

Claim 10

The address decoder circuit of claim 5 wherein each of said word line driving circuits further comprises one or more third enhancement-type MOS transistors through which said one of said first decoder output signals is applied to the gates of said first enhancement-type MOS transistors.