US4656609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1986-04-02
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Granted: 1987-04-07
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Expires: 2006-04-02
Abstract
Abstract A semiconductor memory device includes a redundancy decoder circuit. The redundancy decoder circuit includes FAMOS transistors to which an address pattern, corresponding to an address of a defective memory cell to be replaced by a redundancy memory cell, is written at the floating gates of the FAMOS transistors. The FAMOS transistors are depletion type. Control gates thereof receive a voltage having ground level or lower during a usual memory access mode.
Inventors
- 👤 Mitsuo Higuchi
- 👤 Ryoji Hagihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:27
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/785; G11C29/789
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
210 words
A semiconductor memory device, operatively connected to receive an address input signal, comprising: a memory cell array including memory cells; a decoder circuit, operatively connected to said memory cell array, for accessing a specified one of said memory cells in accordance with the address input signal; a redundancy memory cell, operatively connected to said decoder circuit, for replacing a defective memory cell in said memory cell array; and a redundancy decoder circuit, operatively connected to said decoder circuit, for receiving said address input signal and producing a selection signal for selecting said redundancy memory cell when the received address input signal corresponds to the address of the defective memory cell, said redundancy decoder circuit including a plurality of depletion-type FAMOS transistors, each of said FAMOS transistors being selected or non-selected in accordance with the selection signal and having a floating gate and a control gate, a write operation being performed in each of said selected FAMOS transistors by applying a predetermined voltage to said control gate of each of said FAMOS transistors and by injecting hot electrons into each said floating gate in dependence upon the predetermined voltage applied to said control gate, thereby inducing an electric field beneath the floating gate in a direction which repulses the hot electrons.
Claim 2
Dependent Claim
210 words
A semiconductor memory device, operatively connected to receive an address input signal, comprising: a memory cell array including memory cells; a decoder circuit, operatively connected to said memory cell array, for accessing a specified one of said memory cells in accordance with the address input signal; a redundancy memory cell, operatively connected to said decoder circuit, for replacing a defective memory cell in said memory cell array; and a redundancy decoder circuit, operatively connected to said decoder circuit, for receiving said address input signal and producing a selection signal for selecting said redundancy memory cell when the received address input signal corresponds to the address of the defective memory cell, said redundancy decoder circuit including a plurality of depletion-type FAMOS transistors, each of said FAMOS transistors being selected or non-selected in accordance with the selection signal and having a floating gate and a control gate, a write operation being performed in each of said selected FAMOS transistors by applying a predetermined voltage to said control gate of each of said FAMOS transistors and by injecting hot electrons into each said floating gate in dependence upon the predetermined voltage applied to said control gate, thereby inducing an electric field beneath the floating gate in a direction which repulses the hot electrons.
Claim 3
Dependent Claim
31 words
A semiconductor memory device as set forth in claim 1, wherein said predetermined voltage is set, during an operation mode other than said write operation mode, to ground level or lower.
Claim 4
Dependent Claim
102 words
A semiconductor memory device as set forth in claim 2, further comprising gate transistors having first and second side electrodes and gate electrodes and wherein each of said depletion-type FAMOS transistors having drains, the drains being commonly connected, the control gates being commonly connected, and having sources, respectively, serially connected to said gate transistors at the first side electrodes, the second side electrodes of said gate transistors being grounded, the gate electrodes receive the address input signal so as to make selected ones of said gate transistors conductive and the other said gate transistors nonconductive in accordance with the address input signal.
Claim 5
Dependent Claim
72 words
A semiconductor memory device, operatively connected to receive a write voltage and a power source voltage, as set forth in claim 3, wherein the commonly connected drains of said depletion type FAMOS transistors receive the write voltage during the write operation mode and the power source voltage during a memory access mode and, simultaneously, the control gates of said depletion type FAMOS transistors receive the predetermined voltage having ground level or lower.
Claim 6
Dependent Claim
41 words
A semiconductor memory device as set forth in claim 4, further comprising a transistor pair, operatively connected to the drains of said depletion-type FAMOS transistors, wherein the write voltage and the power source voltage are selectively applied to said transistor pair.
Claim 7
Dependent Claim
29 words
A semiconductor memory device as set forth in claim 1, wherein said predetermined voltage is ground level or lower and is applied only during a memory access mode operation.
Claim 8
Dependent Claim
28 words
A semiconductor memory device as set forth in claim 6, further comprising gate transistors, respectively, operatively connected to said depletion-type FAMOS transistors, for receiving the address input signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-04-06 | 1990-10-06 | 1991-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-04-06 | 1994-10-06 | 1995-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-04-06 | 1998-10-06 | 1999-04-07 | $7700.00 | Window Closed / Lapsed |