Color signal processing circuit

Claim 2

A color signal processing circuit comprising: multiplier means for receiving a first digital chroma signal and a second signal and producing a third signal which represents the multiplication of said first and second signals; means for transmitting said first signal to said multiplier means; matrix coefficient means responsive to said third signal for generating a plurality of matrix coefficients, said matrix coefficient means including a first selector means for selecting said matrix coefficients in time division manner and for producing said second signal; and ACC means, connected between said multiplier means and said matrix coefficient means, for generating an ACC signal upon application of said third signal.

Claim 3

A color signal processing circuit according to claim 1, wherein said transmitting means includes a second selector means which selects said ACC signal during the nonsignal period of said digital chroma signal and selects said digital chroma signal during the burst and video signal periods of said digital chroma signal.

Claim 4

A color signal processing circuit according to claim 1, wherein said matrix coefficient means provides first matrix coefficients and second matrix coefficients; said first selector means selects said first matrix coefficients as said second signal during the nonsignal period of said digital chroma signal and selects said ACC signal as said second signal during the burst signal period of said digital chroma signal and selects said second matrix coefficients during the video period of said digital chroma signal; and wherein said second matrix coefficients are the multiplication of said ACC signal and said first matrix coefficients.

Claim 5

A color signal processing circuit according to claim 3, wherein said matrix coefficient means further includes register means for storing said second matrix coefficients, and includes second selector means for selecting said first matrix coefficients and said second matrix coefficients stored in said register means.

Claim 6

A color signal processing circuit according to claim 4, wherein said matrix coefficient means further comprises, adjusting means for adjusting said first matrix coefficients by an arithmetic operation of ##EQU9## whereby color saturation and hue are controlled, where, RX1, GX1, BX1, RY1, GY1 and BY1 are the first matrix coefficient signals, A1 is the adjust color saturation degree adjustment signal, RX0, GX0, BX0, RY0, GY0, and BY0 are the predetermined first matrix coefficient signals, θ is the hue adjustment signal, and where said second matrix coefficients RX2, GX2, BX2, RY2, GY2, and BY2 are obtained by an arithmetic operation of ##EQU10## where, said A0 is the ACC signal.

Claim 7

A color signal processing circuit according to claim 1, further comprising: delay means connected to said multiplier means for delaying said third signal by a given period and for producing a delayed signal; and means for adding said third signal and delayed signal for producing a color difference signal.

Claim 8

A color signal processing circuit according to claim 1, wherein said transmitting means substantially transmits said digital chroma signal; and said first selector means selects said ACC signal during the burst signal period of said digital chroma signal, and selects said matrix coefficients during the video period of said digital chroma signal.

Claim 9

A color signal processing circuit according to claim 7, wherein said matrix coefficient means comprises; adjusting means for adjusting said matrix coefficients RX, GX, BX, RY, GY and BY by an arithmetic operation of ##EQU11## whereby color saturation and hue are controlled, where, A1 is the color saturation degree adjustment signal, θ is the hue adjustment signal, A0 is the ACC signal, RX0, GX0, BX0, RY0, GY0, and BY0 are the predetermined first matrix coefficient signals.

Claim 10

A color signal processing circuit comprising: multiplier means for receiving a first digital chroma signal and a second signal and producing a third signal which is multiplication of said first and second signals; ACC means connected to said multiplier means for generating an ACC signal in response to said third signal; data selector means for providing matrix coefficients in time division manner; a multiplier for multiplying said matrix coefficients and said ACC signal, and for producing said second signal; adjusting means for adjusting said matrix coefficients W by an arithmetic operation ##EQU12## said multiplier performing an operation of W×A in order to obtain said second signal, where, RXO, GXO, BXO, RYO, GYO, and BYO are the predetermined first matrix coefficient signals, A1 is the color saturation degree adjustment signal, θ is the hue adjustment signal, and A0 is the ACC signal.

Claim 11

A color signal processing circuit comprising: multiplier means for receiving a first digital chroma signal and a second signal and producing a third signal which is multiplication of said first and second signals; ACC means connected to said multiplier means for generating an ACC signal in response to said third signal; data selector means for providing matrix coefficients in time division manner; a multiplier for multiplying said matrix coefficients and said ACC signal, and for producing said second signal; adjusting means for adjusting said matrix coefficients W by an arithmetic operation ##EQU12## said multiplier performing an operation of W×A in order to obtain said second signal, where, RXO, GXO, BXO, RYO, GYO, and BYO are the predetermined first matrix coefficient signals, A1 is the color saturation degree adjustment signal, θ is the hue adjustment signal, and A0 is the ACC signal.

Claim 12

A color signal processing circuit according to claim 9, further comprising; delay means connected to said multiplier means, for delaying said third signal by a given period and for producing a delayed signal, means for adding said third signal and delayed signal, for producing a color difference signal.