Supervisory circuit for a programmed processing unit

Claim 1

A circuit for use in an integrated circuit to supervise the program execution of a processing unit by monitoring a restart signal, generated by said processing unit during the program execution thereof, to identify improper program execution conditions and to attempt to alleviate said improper conditions by generating a reset signal which is supplied to said processing unit to govern the program execution thereof to a prespecified point from which point program execution may continue upon removal of said reset signal, said restart signal being generated within a predetermined duty cycle range under proper program execution conditions and out-of-range under improper program execution conditions, said supervising circuit comprising: circuit means for generating a first signal at a value representative of the apparent range of said restart signal; first circuit means responsive to said first signal and a first reference signal to generate a first control signal when the value of said first signal is greater than the value of said first reference signal; second circuit means responsive to said first signal and a second reference signal to generate a second control signal when the value of said first signal is less than the value of said second reference signal; third circuit means for setting the first reference signal at a first value and the second reference signal at a second value, said first value being greater than said second value; fourth circuit means coupled to said third circuit means and governed by the generated first control signal to cause the first reference signal to change from said first value setting to a third value swtting which is sustained during said first control signal generation, said third value setting being less than said first value setting; fifth circuit means coupled to said third circuit means and governed by the generated second control signal to cause the second reference signal to change from said second value setting to a fourth value setting which is sustained during said second control signal generation, said fourth value setting being greater than said second value setting; sixth circuit means coupled to said first signal generating circuit means and governed by the generated first control signal to cause the first signal to decrease in value at a first predetermined rate during the first control signal generation; seventh circuit means coupled to said first signal generating circuit means and governed by the generated second control signal to cause the first signal to increase in value at a second predetermined rate during the second control signal generation; and circuit means governed by the generated first and second control signals to generate said reset signal.