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US4677741A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing package for high power integrated circuit

Assignee: Mitsubishi Electric Corp
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Filing: 1986-07-10
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Granted: 1987-07-07
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Expires: 2006-07-10
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Abstract

Abstract A semiconductor device is provided within an outer container (21) made of a ceramic which is of a box shape having an opening in an upper portion thereof and a bottom plate and also having a stepped portion (21a) at the position in an intermediate height of an inner wall of side plates. A metalized layer (22) is deposited in inner and outer surfaces of the bottom plate and a surface of the stepped portion. A metal plate (30) is brazed by a silver solder (26) on the metalized layer of the outer surface of the bottom plate and at the same time, a common metal substrate (27) is also brazed by a silver solder (26) on the metalized layer (22) on the inner surface of the bottom plate. A plurality of external electrodes (23, 23', 24, 25) in a frame shape of a conductor plate are connected to the metalized layer (22) of the surface of the stepped portion (21a) by a silver solder (26). A heat sink plate (10 ) is connected to the common metal substrate (27) by means of soldering (6) and a semiconductor chip (7, 28) is soldered on the heat sink plate (10). After a semiconductor chip (7, 28) is electrically connected to the plurality of electrodes (23, 23', 24, 25) and the metal plate (30), the container (21) is filled with a soft resin (12) for sealing.

Inventors

  • 👤 Shinobu Takahama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 05:32
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/30; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W76/40; H10W76/42; H10W76/47; H10W72/381; H10W72/50; H10W72/531; H10W72/5363; H10W72/541; H10W72/547; H10W72/5475; H10W72/551; H10W72/552; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144; Y10T29/49147; Y10T29/49149

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 188 words
A method for manufacturing a semiconductor apparatus comprising the steps of: preparing ceramic outer container in a box shape having an opening in an upper portion thereof and a bottom plate and also having a stepped portion at the position of an intermediate height of an inner wall thereof, forming metalized layers on inner and outer surfaces of said bottom plate and the surface of said stepped portion, brazing by a hard solder a common metal substrate onto the metalized layer on the inner surface of said bottom plate simultaneously with brazing by a hard solder a metal plate onto the metalized layer of the outer surface of said bottom plate, brazing by a hard solder a plurality of external electrodes of a conductor plate frame shape on the metalized layer on the surface of said stepped portion, brazing by a soft solder a heat sink plate on said common metal substrate, brazing by a soft solder a semiconductor chip on said heat sink plate, electrically connecting said semiconductor chip to said metal plate and said external electrodes, and filling a soft sealing resin in said outer container.
Claim 2
Independent Claim 188 words
A method for manufacturing a semiconductor apparatus comprising the steps of: preparing ceramic outer container in a box shape having an opening in an upper portion thereof and a bottom plate and also having a stepped portion at the position of an intermediate height of an inner wall thereof, forming metalized layers on inner and outer surfaces of said bottom plate and the surface of said stepped portion, brazing by a hard solder a common metal substrate onto the metalized layer on the inner surface of said bottom plate simultaneously with brazing by a hard solder a metal plate onto the metalized layer of the outer surface of said bottom plate, brazing by a hard solder a plurality of external electrodes of a conductor plate frame shape on the metalized layer on the surface of said stepped portion, brazing by a soft solder a heat sink plate on said common metal substrate, brazing by a soft solder a semiconductor chip on said heat sink plate, electrically connecting said semiconductor chip to said metal plate and said external electrodes, and filling a soft sealing resin in said outer container.
Claim 3
Dependent Claim 30 words
A method for manufacturing a semiconductor apparatus in accordance with claim 1, wherein said hard solder brazing includes a silver solder brazing and said soft solder brazing includes a soldering.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-07-06 1991-01-05 1991-07-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-07-06 1995-01-05 1995-07-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-07-06 1999-01-05 1999-07-07 $7700.00 Window Closed / Lapsed

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