US4680542A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic circuit tester
Assignee: Individual
•
Filing: 1985-05-22
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Granted: 1987-07-14
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Expires: 2005-05-22
Abstract
Abstract A logic circuit tester wherein high and low threshold signal states and transitions through them are detected. The presence or absence of any of these four states is used to provide combinations of logic signals to an L.E.D. dot matrix display unit encoded to respond with a series of 11 patterns, each of which is illustrative of a circuit state likely to be encountered.
Inventors
- 👤 Gerald L. Krupp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:25
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16557
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
394 words
A logic circuit tester comprising: sampling means for making electrical contacts across a logic circuit and providing a signal output representative of the logic signal present; first circuit means responsive to said signal output for providing one selected signal state as a first discrete electrical output within a selected period when said signal output is representative of a logic signal which is above a selected upper threshold level for at least a selected percentage of the cycle of said logic signal, and a different signal state within said selected period when said signal output is not above said upper threshold level for a said selected percentage of the said cycle of said logic signal; second circuit means responsive to said signal output for providing one selected signal state within said selected period as a second discrete electrical output upon the logic signal passing through said selected upper threshold level in a said cycle, and a different signal state within said selected period when said logic signal does not pass through said selected upper threshold level in a said cycle; third circuit means responsive to said signal output for providing one selected signal state as a third discrete electrical output within said selected period when said signal output is representative of a logic signal which is lower than a selected lower threshold level, which lower threshold level is lower than said upper threshold level, for at least a selected percentage of the cycle of said logic signal, and a different signal state within said selected period when said logic signal is not lower than said selected lower threshold level for at least a selected percentage of the cycle of said logic signal; fourth circuit means responsive to said signal output for providing one selected signal state as a fourth discrete electrical output within a selected period upon the occurrence in a logic cycle of the logic signal passing through said lower threshold level, and a different signal state within said selected period when said logic signal does not pass through said lower threshold level during a logic cycle; and output means responsive to simultaneous said first, second, third, and fourth discrete electrical outputs for electrically combining said electrical signal outputs and distinctively indicating the discrete occurrence of each of a plurality of different combinations of signal states of said first, second, third, and fourth outputs.
Claim 2
Dependent Claim
394 words
A logic circuit tester comprising: sampling means for making electrical contacts across a logic circuit and providing a signal output representative of the logic signal present; first circuit means responsive to said signal output for providing one selected signal state as a first discrete electrical output within a selected period when said signal output is representative of a logic signal which is above a selected upper threshold level for at least a selected percentage of the cycle of said logic signal, and a different signal state within said selected period when said signal output is not above said upper threshold level for a said selected percentage of the said cycle of said logic signal; second circuit means responsive to said signal output for providing one selected signal state within said selected period as a second discrete electrical output upon the logic signal passing through said selected upper threshold level in a said cycle, and a different signal state within said selected period when said logic signal does not pass through said selected upper threshold level in a said cycle; third circuit means responsive to said signal output for providing one selected signal state as a third discrete electrical output within said selected period when said signal output is representative of a logic signal which is lower than a selected lower threshold level, which lower threshold level is lower than said upper threshold level, for at least a selected percentage of the cycle of said logic signal, and a different signal state within said selected period when said logic signal is not lower than said selected lower threshold level for at least a selected percentage of the cycle of said logic signal; fourth circuit means responsive to said signal output for providing one selected signal state as a fourth discrete electrical output within a selected period upon the occurrence in a logic cycle of the logic signal passing through said lower threshold level, and a different signal state within said selected period when said logic signal does not pass through said lower threshold level during a logic cycle; and output means responsive to simultaneous said first, second, third, and fourth discrete electrical outputs for electrically combining said electrical signal outputs and distinctively indicating the discrete occurrence of each of a plurality of different combinations of signal states of said first, second, third, and fourth outputs.
Claim 3
Dependent Claim
22 words
A logic circuit tester as set forth in claim 1 wherein said output means comprises display means for providing a visual presentation.
Claim 4
Dependent Claim
67 words
A logic circuit tester as set forth in claim 2 wherein said second and fourth circuit means are responsive to a said signal passing through a said threshold for providing a said one signal state for a period exceeding a cycle of said logic signal, and whereby said display means is enabled to provide a longer time display of such event that the time of its occurrence.
Claim 5
Dependent Claim
17 words
A logic circuit tester as set forth in claim 3 wherein said selected percentage is approximately 50%.
Claim 6
Dependent Claim
54 words
A logic circuit tester as set forth in claim 4 wherein said display means comprises a matrix of X by Y light sources having X and Y line inputs and includes logic means responsive to said first, second, third, and fourth outputs for selectively energizing discrete said light sources for forming discrete light patterns.
Claim 7
Dependent Claim
101 words
A logic circuit tester as set forth in claim 5 wherein said logic means comprises: counting means for providing a recycling count of up to at least X; drive means responsive to said counting means for sequentially, and on a recycling basis, providing a first electrical input to each X line of said matrix of light sources; and memory means responsive to said first, second, third, and fourth outputs and said recycling count for selectively providing a second potential to discrete light sources in a selected Y line of said matrix of light sources; whereby said discrete light patterns are formed.
Claim 8
Dependent Claim
130 words
A logic circuit tester as set forth in claim 6 wherein: said tester includes an elongated housing enclosing said circuit means and said display, said housing having an opening through which said display is viewable, with the X lines of said matrix of light sources being generally parallel with the longitudinal dimension of said housing; said sampling means includes an electrical probe extending from one end of said housing; and said logic means includes position responsive switching means for inverting said patterns as a function of the orientation of said housing wherein, when said housing is being held generally with said probe to the left of a viewer, said pattern will appear the same as when said probe is being held with said pattern to the right of a viewer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-07-13 | 1991-01-12 | 1991-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-07-13 | 1995-01-12 | 1995-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-07-13 | 1999-01-12 | 1999-07-14 | $7700.00 | Window Closed / Lapsed |