Patent US4688323A successfully refreshed from Google Patents.
US4688323A
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Method for fabricating vertical MOSFETs
Assignee: Hitachi Ltd
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Filing: 1985-10-31
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Granted: 1987-08-25
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Expires: 2005-10-31
Abstract
Abstract A method for fabrication a vertical MOSFET which contains a protective element for protecting the gate electrode of an insulated gate field effect transistor. The protective element is formed of the same semiconductor layer as that of the gate electrode of the insulated gate field effect transistor and is formed integrally with the gate electrode on an insulating film formed on the surface of a semiconductor substrate.
Inventors
- 👤 Isao Yoshida
- 👤 Takeaki Okabe
- 👤 Mitsuo Ito
- 👤 Kazutoshi Ashikawa
- 👤 Tetsuo Iijima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:19
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/101; H10D84/141; H10D84/148; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/665; H10D89/00; H10D89/60; H10D89/601; H10D89/611; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D8/00; H10D8/20; H10D8/25
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
215 words
A method of fabricating a vertical MOSFET comprising the steps of: (a) forming an insulating film having a first insulating film portion and a second insulating film portion, thinner than said first insulating film portion, on the surface of a semiconductor substrate of a first conductivity type which is to serve as a drain portion; (b) forming a first semiconductor layer portion on said first insulating film portion and a second semiconductor layer portion on said second insulating film portion, respectively; (c) introducing an impurity of the second conductivity type into said semiconductor substrate using a part of said second semiconductor layer portion as a mask so as to form a second conductivity type region which is to serve as a channel portion, while introducing an impurity of the second conductivity type into said first semiconductor layer portion; and (d) introducing an impurity of the first conductivity type into said second conductivity type region using a part of said second semiconductor layer portion as a mask so as to form a first conductivity type region to serve as a source region, while selectively introducing an impurity of the first conductivity type into said second semiconductor layer portion, so as to form P-N junctions to serve as a protective element inside said second semiconductor layer portion.
Claim 2
Independent Claim
215 words
A method of fabricating a vertical MOSFET comprising the steps of: (a) forming an insulating film having a first insulating film portion and a second insulating film portion, thinner than said first insulating film portion, on the surface of a semiconductor substrate of a first conductivity type which is to serve as a drain portion; (b) forming a first semiconductor layer portion on said first insulating film portion and a second semiconductor layer portion on said second insulating film portion, respectively; (c) introducing an impurity of the second conductivity type into said semiconductor substrate using a part of said second semiconductor layer portion as a mask so as to form a second conductivity type region which is to serve as a channel portion, while introducing an impurity of the second conductivity type into said first semiconductor layer portion; and (d) introducing an impurity of the first conductivity type into said second conductivity type region using a part of said second semiconductor layer portion as a mask so as to form a first conductivity type region to serve as a source region, while selectively introducing an impurity of the first conductivity type into said second semiconductor layer portion, so as to form P-N junctions to serve as a protective element inside said second semiconductor layer portion.
Claim 3
Dependent Claim
41 words
A method of fabricating a vertical MOSFET according to claim 1, wherein the quantity of said impurity of the second conductivity type introduced in step (c) is within the range of 10 13 atoms/cm 2 to 10 15 atoms/cm 2 .
Claim 4
Dependent Claim
63 words
A method of fabricating a vertical MOSFET according to claim 1, wherein step (a) includes the step of introducing an impurity of said second conductivity type into respective first and second surface portions of said substrate on which said first and second insulating film portions are formed, thereby forming respective first and second well regions of said second conductivity type in said substrate.
Claim 5
Dependent Claim
36 words
A method of fabricating a vertical MOSFET according to claim 3, wherein step (c) comprises introducing said impurity of the second conductivity type to form said second conductivity type region contiguous with said second well region.
Claim 6
Dependent Claim
27 words
A method of fabricating a vertical MOSFET according to claim 3, wherein step (b) comprises forming said first semiconductor layer portion to overlie said first well region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-24 | 1991-02-23 | 1991-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-24 | 1995-02-23 | 1995-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-24 | 1999-02-23 | 1999-08-25 | $7700.00 | Window Closed / Lapsed |