Patent US4689501A successfully refreshed from Google Patents.
US4689501A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal level detector for compact disc player
Assignee: US Philips Corp
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Filing: 1986-01-21
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Granted: 1987-08-25
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Expires: 2006-01-21
Abstract
Abstract For detecting whether an input signal is above or below a reference level in such a way that brief signal interruptions and negative spurious pulses are not interpreted as decreases below the reference level, the detector includes an input comparator, a first delay circuit, a second delay circuit and an output circuit. The first delay circuit comprises a first integrator comprising a first transistor and a first capacitor, a first current source and a second comparator. The second delay circuit comprises a second integrator with a second transistor and a second capacitor, a second current source and a third comparator. The first delay circuit and the second delay circuit have equal delay times. In order to ensure that during detection of a decrease below the reference level a positive spurious pulse is not interpreted as an increase above the reference level a third Transistor connects a third current source in parallel with the first current source of the first delay circuit when the input signal lies below the reference level, so that the delay time of the first delay circuit becomes smaller than that of the second delay circuit.
Inventors
- 👤 Franciscus A. C. M. Schoofs
- 👤 Martinus P. M. Bierhoff
- 👤 Job F. P. van Mil
- 👤 Albert H. Slomp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:11
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16566; G01R19/16585; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; H; H03; H03K; H03K5/00; H03K5/19
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
307 words
A level detector having an input for receiving an input signal and an output for supplying an output signal, comprising a first input comparator having an input and an output, for comparing the level of the input signal with a reference level, which input is coupled to the input of the level detector, a first delay circuit for starting the output signal if the level of the input signal decreases below the reference level during a first time interval, which delay circuit comprises a first integrator comprising a first capacitor arranged between an input and an output of the integrator, which input is coupled to the output of the input comparator and which output is coupled to a first current source and to a first input of a second comparator which has a second input for receiving a reference potential and an output, a second delay circuit for stopping the output signal if the level of the input signal exceeds the reference level during a second time interval, which delay circuit comprises a second integrator comprising a second capacitor arranged between an input and an output of the integrator, which input is coupled to the output of the second comparator and which output is coupled to a second current source and to a first input of a third comparator having a second input for carrying a reference potential and on output which is coupled to the output of the level detector, characterized in that the first time interval and the second time interval are substantially equal to each other, in that a switchable third current source is arranged in parallel with the first current source, and in that the level detector is provided with switching means for switching on the third current source if the output of the third comparator of the second delay circuit is currentless.
Claim 2
Dependent Claim
307 words
A level detector having an input for receiving an input signal and an output for supplying an output signal, comprising a first input comparator having an input and an output, for comparing the level of the input signal with a reference level, which input is coupled to the input of the level detector, a first delay circuit for starting the output signal if the level of the input signal decreases below the reference level during a first time interval, which delay circuit comprises a first integrator comprising a first capacitor arranged between an input and an output of the integrator, which input is coupled to the output of the input comparator and which output is coupled to a first current source and to a first input of a second comparator which has a second input for receiving a reference potential and an output, a second delay circuit for stopping the output signal if the level of the input signal exceeds the reference level during a second time interval, which delay circuit comprises a second integrator comprising a second capacitor arranged between an input and an output of the integrator, which input is coupled to the output of the second comparator and which output is coupled to a second current source and to a first input of a third comparator having a second input for carrying a reference potential and on output which is coupled to the output of the level detector, characterized in that the first time interval and the second time interval are substantially equal to each other, in that a switchable third current source is arranged in parallel with the first current source, and in that the level detector is provided with switching means for switching on the third current source if the output of the third comparator of the second delay circuit is currentless.
Claim 3
Dependent Claim
155 words
A level detector as claimed in claim 1, characterized in that the second comparator comprises a first transistor of a first conductivity type having an emitter, a base and a collector, the emitter constituting the first input, the base constituting the second input and the collector constituting the output, and the third comparator comprises a second transistor of the first conductivity type having an emitter, a base and a first and second collector the emitter constituting the first input, the base constituting the second input and the first collector constituting the output, and in that the switching means comprise a third transistor of a second conductivity type opposite to the first conductivity type, having a base, an emitter and a collector, the base being connected to the second collector of the second transistor and the collector being connected to the third current source and, via a diode, to the output of the first delay circuit.
Claim 4
Dependent Claim
153 words
A level detector as claimed in claim 1, wherein said first integrator comprises a first integrator transistor of the second conductivity type having a base, an emitter and a collector, the base being connected to the output of the input comparator, the emitter being connected to a point carrying a reference potential, and the collector being connected to the first current source; and wherein said second integrator comprises a second integrator transistor of the second conductivity type having a base, an emitter and a collector, the base being connected to the output of the second comparator, the emitter being connected to the point carrying a reference potential, and the collector being connected to the second current source, and in that the first current source, the second current source and the third current source each supply an output current which is proportional to the current-gain factor of a transistor of the second conductivity type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-24 | 1991-02-23 | 1991-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-24 | 1995-02-23 | 1995-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-24 | 1999-02-23 | 1999-08-25 | $7700.00 | Window Closed / Lapsed |