Patent US4692902A successfully refreshed from Google Patents.
US4692902A
Expired / Lapsed
US
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Semiconductor read only memory device with improved access time
Assignee: Toshiba Corp
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Filing: 1984-09-25
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Granted: 1987-09-08
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Expires: 2004-09-25
Abstract
Abstract A semiconductor memory device in which the differential amplifier circuit compares a potential of a bit line to which memory cells storing information are connected with a reference potential of a dummy line to which a dummy cell is connected, and detects information stored in each of the memory cells. The semiconductor memory device comprises a circuit which discharges both the bit line and the dummy line to a low potential when the chip enable inverted signal is supplied. When the chip enable signal is supplied, therefore, the differential amplifier circuit can detect a difference between the bit line potential and the dummy line potential before the bit line is fully charged up. This makes it possible to produce the chip enable access time and to realize higher speed operations.
Inventors
- 👤 Sumio Tanaka
- 👤 Shinji Saito
- 👤 Shigeru Atsumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:15
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C7/06; G11C7/062; G11C7/12; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
136 words
A semiconductor memory device comprising: memory cells storing information; a bit line connected to said memory cells; static-type differential amplifier means havig a first input temrinal at which the potential of said bit line is fed as an input, a second input terminal at which a reference potential is fed as an input, and an output temrinal independent of said first and second input terminals, said differential amplifier means comparing potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means responsive to a chip enable inverted signal for discharging said bit line to a predetermined potential level; and second means responsive to said chip enable inverted signal for discharging said reference potential to substantially the same level as said predetermined potential level.
Claim 2
Dependent Claim
136 words
A semiconductor memory device comprising: memory cells storing information; a bit line connected to said memory cells; static-type differential amplifier means havig a first input temrinal at which the potential of said bit line is fed as an input, a second input terminal at which a reference potential is fed as an input, and an output temrinal independent of said first and second input terminals, said differential amplifier means comparing potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means responsive to a chip enable inverted signal for discharging said bit line to a predetermined potential level; and second means responsive to said chip enable inverted signal for discharging said reference potential to substantially the same level as said predetermined potential level.
Claim 3
Dependent Claim
80 words
A semiconductor memory device as claimed in claim 1, in which said first means comprises an n-channel FET having a drain connected to said first input terminal of said differential amplifier means, a source grounded, and a gate supplied with the chip enable inverted signal and said second means comprises an n-channel FET having a drain connected to said second input terminal of said differential amplifier means, a source grounded, and a gate supplied with the chip enable inverted signal.
Claim 4
Dependent Claim
90 words
A semiconductor memory device as claimed in claim 2, in which said differential amplifier means further comprises: first and second n-channel FETs having gates connected to said first and second input terminals respectively and sources connected with each other; first and second p-channel FETs having drains connected to the drains of said first and second n-channel FETs respectively, gates both connected to the drain of said second n-channel FET, and sources both connected to a power supply; and an output terminal connected to the drain of said first n-channel FET.
Claim 5
Dependent Claim
141 words
A semiconductor memory device comprising: memory cells storing information; a bit line connected to said memory cells; a dummy cell storing dummy information; a dummy line connected to said dummy cell; static type differential amplifier means having a first input terminal at which said bit line is connected, a second input terminal at which said dummy line is connected, and an output terminal independent of said first and second input temrinals, said differential amplifier means comparing potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means responsive to a chip enable inverted signal for discharging said bit line to a predetermined potential elve; and second means responsive to said chip enable inverted signal for discharging said dummy line to substantially the same level as said predetermined potential.
Claim 6
Dependent Claim
141 words
A semiconductor memory device comprising: memory cells storing information; a bit line connected to said memory cells; a dummy cell storing dummy information; a dummy line connected to said dummy cell; static type differential amplifier means having a first input terminal at which said bit line is connected, a second input terminal at which said dummy line is connected, and an output terminal independent of said first and second input temrinals, said differential amplifier means comparing potentials fed at said first and second input terminals with each other and detecting information stored in each of said memory cells; first means responsive to a chip enable inverted signal for discharging said bit line to a predetermined potential elve; and second means responsive to said chip enable inverted signal for discharging said dummy line to substantially the same level as said predetermined potential.
Claim 7
Dependent Claim
85 words
A semiconductor memory device as claimed in claim 4, in which said first means comprisea an n-channel FET having a drain connected to said first input terminal of said differential amplifier means, a source grounded, and a gate supplied as inptu with the chip enable inverted signal and said second means comprises an n-channel FET having a drain connected to said second input terminal of said differential amplifier means, a source grounded, and a gate supplied as an iput with the chip enable inverted signal.
Claim 8
Dependent Claim
90 words
A semiconductor memory device as claimed in claim 5, in which said differential amplifier means further comprises: first and second n-channel FETs having gates connected to said first and second input terminals respectively and sources connected with each other; first and second p-channel FETs having drains connected to the drains of said first and second n-channel FETs respectively, gates both connected to the drain of said second n-channel FET, and sources both connected to a power supply; and an output terminal connected to the drain of said first n-channel FET.
Claim 9
Dependent Claim
71 words
A semiconductor memory device as claimed in claim 5, which further comprises: first and second intrinsic n-channel FETs having sources connected to said first and second input terminals respectively and gates supplied with the power supply; and first and second p-channel FETs having drains connected to said first and second intrinsic n-channel FETs respectively, gates supplied as inputs with the chip enable inverted signal, and sources supplied with the power supply.
Claim 10
Dependent Claim
71 words
A semiconductor memory device as claimed in claim 5, which further comprises: first and second p-channel FETs having drains connected to said first and second input terminals respectively and gates and drains connected to each other respectively; and first and second p-channel FETs having drains connected to said first and second p-channel FETs, gates supplied as inputs with the chip enable inverted signal, and sources both supplied with the power supply.
Claim 11
Dependent Claim
91 words
A semiconductor memory device as claimed in claim 5, which further comprises: a first bias circuit inserted between the first input terminal of said differential amplifier means and said bit line, said first bias circuit biasing the potential of said bit line so that said potential assumes either of predetermined values; and a second bias circuit inserted between said second input terminal of said differential amplifier means and said dummy line, said second bias circuit biasing the potential of said dummy line so that said potential assumes either of predetermined values.
Claim 12
Dependent Claim
91 words
A semiconductor memory device as claimed in claim 6, which further comprises: a first bias circuit inserted between the first input temrinal of said differential amplifier means and said bit line, said first bias circuit biasing the potential of said bit line so that said potential assumes either of predetermined values; and a second bias circuit inserted between said second input terminal of said differential amplifier means and said dummy line, said second bias circuit biasing the potential to said dummy line so that said potential assumes either of predetermined values.
Claim 13
Dependent Claim
144 words
In a semiconductor memory device having memory cells storing information therein, a bit line connected to said memory cells, a differential amplifier means having a first input terminal at which the potential of said bit line is fed as an input, a second input terminal at which a reference potential is fed as in input, and an output terminal independent of said first and second input terminals, the differential amplifier means comparing potentials fed at the first and second input terminals with each other and detecting information stored in each of the memory cells, a method of reducing chip enable access time comprising the steps of: discharging said bit line to a predetermined potential level in response to a chip non-enable signal; and discharging said refeence potential to substantially the same level as said predetermined potential level in response to said chip non-enable signal.
Claim 14
Dependent Claim
144 words
In a semiconductor memory device having memory cells storing information therein, a bit line connected to said memory cells, a differential amplifier means having a first input terminal at which the potential of said bit line is fed as an input, a second input terminal at which a reference potential is fed as in input, and an output terminal independent of said first and second input terminals, the differential amplifier means comparing potentials fed at the first and second input terminals with each other and detecting information stored in each of the memory cells, a method of reducing chip enable access time comprising the steps of: discharging said bit line to a predetermined potential level in response to a chip non-enable signal; and discharging said refeence potential to substantially the same level as said predetermined potential level in response to said chip non-enable signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-09-07 | 1991-03-09 | 1991-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-09-07 | 1995-03-09 | 1995-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-09-07 | 1999-03-09 | 1999-09-08 | $7700.00 | Window Closed / Lapsed |