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US4698747A
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Instruction address calculation unit for a microprocessor
Assignee: NXP USA Inc
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Filing: 1985-06-28
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Granted: 1987-10-06
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Expires: 2005-06-28
Abstract
Abstract An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.
Inventors
- 👤 Robert R. Thompson
- 👤 David S. Mothersole
- 👤 Douglas B. MacGregor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 09:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
157 words
An execution unit for use in a microprocessor, comprising: a data section for performing arithmetic and logic operations on data, an address section for generating data addresses, a program section for generating instruction addresses, a data bus having a data segment selectively coupleable to the data section of the execution unit, an address segment selectively coupleable to the address section of the execution unit, and a program segment selectively coupleable to the program section of the execution unit, the data and program segments of the data bus being selectively coupleable to the address segment thereof; and an address bus having a data segment selectively coupleable to the data section of the execution unit, an address segment selectively coupleable to the address section of the execution unit, and a program segment selectively coupleable to the program section of the execution unit, the data and program segments of the address bus being selectively coupleable to the address segment thereof.
Claim 2
Dependent Claim
157 words
An execution unit for use in a microprocessor, comprising: a data section for performing arithmetic and logic operations on data, an address section for generating data addresses, a program section for generating instruction addresses, a data bus having a data segment selectively coupleable to the data section of the execution unit, an address segment selectively coupleable to the address section of the execution unit, and a program segment selectively coupleable to the program section of the execution unit, the data and program segments of the data bus being selectively coupleable to the address segment thereof; and an address bus having a data segment selectively coupleable to the data section of the execution unit, an address segment selectively coupleable to the address section of the execution unit, and a program segment selectively coupleable to the program section of the execution unit, the data and program segments of the address bus being selectively coupleable to the address segment thereof.
Claim 3
Dependent Claim
24 words
An execution unit as set forth in claim 1 wherein the third section includes an adder for performing arithmetic operations on the instruction addresses.
Claim 4
Dependent Claim
22 words
An execution unit as set forth in claim 2 further comprsing means for selectively providing the instruction address to a cache memory.
Claim 5
Dependent Claim
23 words
An execution unit as set forth in claim 3 further comprising means for simultaneously providing the instruction address to an external address means.
References Cited (Backward Citations)
US4342078A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |