Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction

Abstract

Abstract A bit sliced decimal adding/subtracting unit includes an 8-digit decimal adder/subtracter and an offset data generator. In the 8-digit decimal adder/subtracter, eight 1-digit decimal adder/subtracters are intercoupled so as to allow a carry to propagate from the lower order digit to the higher order digit. The offset data generator has first and second logical gates. The first logical gate detects whether or not an addition mode is specified by operation mode data. The second logical gate determines that a signal ZONE representing the format of the data to be operated represents a zone format, and that the addition mode is detected by said first logical gate. The output signal from the first logical gate is used for the first and second bits of the first 4-bit offset data. The output signal from the second logical gate is used for the 0th bit (MSB) and the third bit (LSB) of the first offset data. The output signal from the first logical gate is also used for the first and second bits of second 4-bit offset data. The 0th bit and the third bit of the second offset data are fixed at logical 0. The first offset data is supplied to the offset inputs of the adder/subtracters at the even digits (where the most significant digit is the 0th digit, and the least significant digit is the seventh digit) of the eight 1-digit decimal adder/subtracters. The second offset data is supplied to the offset inputs of the adder/subtracters at the odd number digits of the eight 1-digit decimal adder/subtracters.

Inventors

• 👤 Tadashi Ishikawa
• 👤 Kazutoshi Eguchi

Bibliographic Details