Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses

Claim 1

A bit interleaved multiplexer system which provides byte synchronization for apparatuses communicating on channels therein, comprising: (a) a multiplexer having (1) a transmit frame including at least one recirculating counter and a memory means, wherein said recirculating counters address the memory means, and the memory means is programmed according to a framing algorithm which frames at least data from said apparatuses and multiplexer framing synchronization information, (2) a plurality of transmit data buffers for accumulating bits of information from their respective apparatuses, wherein a transmit data buffer sends a bit of information for transmission when said transmit frame selects a channel associated with said transmit data buffer according to said framing algorithm, (3) a plurality of transmit mark buffers, wherein when said transmit frame selects a channel, a bit of information is written into the transmit mark buffer for the selected channel, the value of said bit having a first value when a predetermined bit of a byte as defined by said framing algorithm is selected according to said frame, and having a second value when a bit other than said predetermined bit of a byte as defined by said framing algorithm is selected, and wherein when a bit of information exits a transmit mark buffer, the terminal associated therewith sends a bit of information into its respective transmit data buffer, said bit being said predetermined bit of a byte when the exiting bit has said first value; (b) a demultiplexer having (1) a receive frame including at least one recirculating counter and a memory means, wherein the recirculating counters address the memory means, and the memory means is programmed according to a second framing algorithm which demultiplexes at least data and framing synchronization information received from said multiplexer, wherein said framing synchronization information is used to synchronize said transmit and receive frames of said multiplexer and demultiplexer, (2) a plurality of receive data buffers for accumulating bits of information selected by said receive frame and sending them to their respective apparatuses, (3) a plurality of receive mark buffers, wherein when a bit of information is written into the receive data buffer for an apparatus, an addition bit is written into said receive mark buffer, the value of said additional bit having a first value when said predetermined bit of a byte as defined by said second framing algorithm of said demultiplexer is indicated by said receive frame, and having a second value when a bit other than said predetermined bit as defined by receive frame is indicated, and wherein when a bit of information exits a receive mark buffer together with a bit exiting a receive data buffer, the apparatus associated therewith is informed as to whether said bit exiting said receive data buffer is said predetermined bit of the byte according to the value of the bit leaving said receive mark buffer; and (c) at least one aggregate line connecting said multiplexer and demultiplexer over which multiplexed data and framing synchronization information is transmitted, wherein the cumulative delay between the request of a particular bit by said transmit frame and the sending of the requested bit over said aggregate line equals I(L)+C bits, where I is an integer greater than zero, L is the number of bits in a byte, and C is a constant which determines a phase shift between the synchronized transmit and receive frames.