Patent US4721684A successfully refreshed from Google Patents.
US4721684A
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Method for forming a buried layer and a collector region in a monolithic semiconductor device
Assignee: STMicroelectronics SRL
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Filing: 1985-12-20
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Granted: 1988-01-26
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Expires: 2005-12-20
Abstract
Abstract A method for forming a buried layer below the collector region of a transistor of an integrated circuit uses a second doping agent (e.g.--small amounts of phosphorus) in addition to a main doping agent (e.g.--antimony). The use of the second doping agent solves the problem of undesired intermediate or phantom layers caused by the external diffusion (i.e.--out-diffusion) of the doping agent in a P-type doped isolation layer below the buried layer. The use of the second doping agent also solves the problem of providing a collector region for transistors of the integrated circuit with a concentration of impurities which is typically 10 times higher than that of the collector region of a power transistor integrated monolithically on the same chip. The use of the second doping agent finally makes it possible to achieve collector regions for the transistors of the integrated circuit with a concentration of impurities which differs from transistor to transistor in accordance with the circuit functions to be carried out.
Inventors
- 👤 Salvatore Musumeci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:12
CPC Classifications
H; H10; H10P; H10P32/00; H10P32/10; H10P32/15; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
411 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power trnsistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming, within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor.
Claim 2
Independent Claim
411 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power trnsistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming, within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor.
Claim 3
Independent Claim
445 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power transistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein the second and third doping agents comprise antimony and phosphorus at a proportion of one to ten parts of phosphorus per hundred parts of antimony, and wherein the first doping agent comprises boron; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor.
Claim 4
Independent Claim
445 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power transistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein the second and third doping agents comprise antimony and phosphorus at a proportion of one to ten parts of phosphorus per hundred parts of antimony, and wherein the first doping agent comprises boron; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor.
Claim 5
Independent Claim
450 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power transistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming, within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor; wherein the ratio between the concentrations of impurities in the collector region of high resistivity of the power transistor and in each collector region of the transistors of the integrated circuit have a value of between 0.01 and 1.0.
Claim 6
Independent Claim
450 words
A method for the manufacture of a semiconductor device comprising at least one power transistor and a control circuit integrated on a same chip of semiconductor material comprising the following steps: preparing a first layer of monocrystalline silicon of a first type of conductivity; forming, by doping of the first layer with a first doping agent, of a first region of a second type of conductivity which is opposite to the first type of conductivity; forming at least a second region in the first region by doping with impurities of the first type of conductivity; forming, by epitaxial growth, of a second layer of the first type of conductivity and having a high resistivity, the second layer completely covering the first layer and the first region; forming at least one isolation region of the second type of conductivity which passes through the second layer until it reaches the first region and includes within itself at least one portion of the second layer lying above one of the second regions; forming at least one region of the second type of conductivity in the second layer, this at least one region forming a base of a power transistor; forming a region of the first type of conductivity in the base region, this region forming an emitter of the power transistor; forming, within the portions of the second layer confined by the isolation regions, of additional regions forming active and passive components of the integrated circuit; forming electrodes on surfaces of the chip and metal interconnection paths between the active and passive components of the integrated circuit and the power transistor; wherein the formation of the second region includes the pre-deposition or implantation and the subsequent diffusion of a second and a third doping agent of the same type of conductivity and having diffusion coefficients which are respectively higher and lower than the coefficient of the first doping agent; wherein in at least one of the portions of the second layer bounded by an isolation region lying above one of the second regions, atoms of phosphorus are deposited or implanted and then caused to diffuse such that the concentration of all of the doping agents in the portion forming the collector region of a transistor of the integrated circuit is substantially constant and higher in value than the concentration of the single doping agent in the first layer and in the second layer of high resistivity forming the collector region of the power transistor; wherein the ratio between the concentrations of impurities in the collector region of high resistivity of the power transistor and in each collector region of the transistors of the integrated circuit have a value of between 0.01 and 1.0.
Claim 7
Dependent Claim
46 words
A method as claimed in claim 2, wherein the ratio between the concentrations of impurities in the collector region of high resistivity of the power transistor and in each collector region of the transistors of the integrated circuit have a value of between 0.01 and 1.0.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |