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US4722009A
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Tone restoring apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1986-04-01
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Granted: 1988-01-26
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Expires: 2006-04-01
Abstract
Abstract In a tone-restoring apparatus, a first and a second hold circuit latch at a period of 2T data signals read from a digital memory in response to a first and a second address supplied to the digital memory, and a first and a second multiplier circuit multiply the data signals latched in the first and second hold circuit by a monotonically increasing weighting function W1(x) (0</=x</=NT, 0</=W1(x)</=1) or a monotonically increasing weighting function W2(x) (0</=x</=NT, 0</=W2(x)</=1). An adder circuit adds the output signals from the first and second multiplier circuits to each other.
Inventors
- 👤 Yasutoshi Nakama
- 👤 Masayuki Misaki
- 👤 Seiichi Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:05
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B27/00; G11B27/005; G10; G10L; G10L21/00; G10L21/04; G11B20/00007; G11B2220/00; G11B2220/90
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
192 words
A tone-restoring apparatus comprising: an analog-to-digital converter circuit for converting an input signal to a digital signal by sampling said input signal at a period satisfying a sampling rule, and supplying said digital signal to a digital memory in which said digital signal is stored; a write/read control circuit for producing a write/read control signal to specify a write/read address to said digital memory and to control said digital memory to write and read in response to input address data generated from a write address generator and first and second read address generator circuits; first and second hold circuits for latching at a period of 2T signals read from said digital memory in response to first and second read addresses to said digital memory; first and second multiplier circuits for multiplying said signals latched in said first and second hold circuits by a monotonically increasing weighting function W1(x) (0≦x≦NT, 0≦W1(x)≦1) or a monotonically decreasing weighting function W2(x) (0≦x≦NT, 0≦W2(x)≦1); an adder circuit for adding the output signals from said first and second multiplier circuits; and a digital-to-analog converter circuit for converting the output signal from said adder circuit to an analog signal.
Claim 2
Dependent Claim
192 words
A tone-restoring apparatus comprising: an analog-to-digital converter circuit for converting an input signal to a digital signal by sampling said input signal at a period satisfying a sampling rule, and supplying said digital signal to a digital memory in which said digital signal is stored; a write/read control circuit for producing a write/read control signal to specify a write/read address to said digital memory and to control said digital memory to write and read in response to input address data generated from a write address generator and first and second read address generator circuits; first and second hold circuits for latching at a period of 2T signals read from said digital memory in response to first and second read addresses to said digital memory; first and second multiplier circuits for multiplying said signals latched in said first and second hold circuits by a monotonically increasing weighting function W1(x) (0≦x≦NT, 0≦W1(x)≦1) or a monotonically decreasing weighting function W2(x) (0≦x≦NT, 0≦W2(x)≦1); an adder circuit for adding the output signals from said first and second multiplier circuits; and a digital-to-analog converter circuit for converting the output signal from said adder circuit to an analog signal.
Claim 3
Dependent Claim
212 words
A tone-restoring apparatus according to claim 1, wherein 2N signals d 0 , d 1 , d 2 , . . . , d 2N-1 are stored in said digital memory at a period of T from a reference time t=0, the N signals d 0 , d 1 , d 2 , . . . , d N-1 are read from said digital memory and held in said first hold circuit at a period of 2T during a time t, 0≦t<2NT, the N signals d N , d N+1 , d N+2 , . . . , d 2N-1 are read from said digital memory and held in said second hold circuit at a period of 2T during NT≦t<3NT, the output signal from said first hold circuit is multiplied by W 1 (t) during the time t, 0≦t≦NT and W 2 (t-NT) during the time t, NT≦t≦2NT in said first multiplier circuit, and the output from said second hold circuit is multiplied by W 2 (t) during the time t, 0≦t≦NT and W 1 (t-NT) during the period t, NT≦t≦2NT in said second multiplier circuit, the multiplying coefficients of said multipliers being controlled by an amplitude control circuit, said writing, reading and amplitude control being repeated at a period of 2NT.
Claim 4
Dependent Claim
32 words
A tone-restoring apparatus according to claim 1, wherein an adaptive delta modulation system is used for the analog-to-digital conversion, and the amplitude control is made by a one-bit adaptive digital-to-analog converter circuit.
Claim 5
Dependent Claim
79 words
A tone-restoring apparatus according to claim 1, wherein an adaptive delta modulation system is used for the analog-to-digital conversion, this modulation system using a delta modulator having a compression-and-expansion circuit that changes the output of an integrator by increasing the quantization step width when a plurality of the delta modulated digital data of one bit, "1" or "0" occur in sequence, and the adaptive quantization step width is determined by a pulse width modulator circuit in the delta modulator.
Claim 6
Dependent Claim
29 words
A tone-restoring apparatus according to claim 4, wherein said pulse width modulator circuit employs a linear pulse-width modulator circuit for linearly converting the pulse count to a pulse width.
Claim 7
Dependent Claim
29 words
A tone-restoring apparatus according to claim 4, wherein said pulse width modulator circuit employs a nonlinear pulse-width modulator circuit for nonlinearly converting the pulse count to a pulse width.
Claim 8
Dependent Claim
25 words
A tone-restoring apparatus according to claim 4, wherein the multiplier and multiplicand in said first and second multiplier circuits are both a pulse-width modulated signal.
Claim 9
Dependent Claim
148 words
An adaptive delta modem according to claim 3, wherein said adaptive delta modulator comprises: a comparator for comparing an analog input signal with a fed-back signal; a sampling circuit for producing a digital signal of one bit; a quantization step width adaptive logic circuit; an m-bit up/down counter; a decoder for decoding an m-bit output to n bits; a pulse width modulator circuit for converting an n-bit output from said decoder to a pulse width; a polarity switching circuit for switching the output from said pulse-width modulating circuit between positive and negative polarities; and an integrator circuit for integrating the output from said polarity switching circuit, thereby converting it to an analog signal, and producing said fed-back signal, said adaptive delta demodulator comprises the same components as those of said adaptive delta modulator except said comparator, and a low pass filter at the output of said integrator circuit.
Claim 10
Dependent Claim
40 words
An adpative delta modem according to claim 8, wherein a pulse-width modulator circuit for converting the output from said m-bit up/down counter to a pulse width is used instead of said decoder for converting an m-bit output to n bits.
References Cited (Backward Citations)
US4620238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |