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US4738933A Expired / Lapsed US ⏱️ 0.0 years remaining

Monolithic PIN diode and method for its manufacture

Assignee: Fei Microwave Inc
•
Filing: 1985-08-27
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Granted: 1988-04-19
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Expires: 2005-08-27
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Abstract

Abstract A monolithic semiconductor device that provides a diode having PIN diode characteristics. The diode has anode and cathode mesas having contacts in substantially the same plane to facilitate automatic bonding. One of the contacts is insulated from its associated mesa and has a conductive layer that extends between the mesas and through an insulating layer to make direct contact with the substrate, thereby isolating the flow of current from any intervening I regions. The conductive layer may include a portion of narrow cross section, to function as a fuse.

Inventors

  • 👤 John G. Richards

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 11:57
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/50; H10D8/422; H10D84/00; H10D84/201; H10D84/204; H10D84/221

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 161 words
A method of fabricating a monolithic PIN diode in a wafer of semiconductor material having a substrate that forms a first a majority charge region and an overlying layer that forms an I region, the method comprising the steps of: removing the overlying layer from the substrate around each of two predefined areas whereby the remaining overlying layer forms first and second I region mesas on the substrate, each mesa having an upper surface; forming a second majority charge region in the upper portion of the second mesa, the second majority charge region being of opposite polarity to the first majority charge region, and separated from the first majority charge region by the intervening I region of the second mesa; applying insulation to the exposed surfaces of the mesas and the substrate, the insulation having a first opening located between the mesas for access to the substrate, and a second opening for access to the upper surface of the second mesa;
Claim 2
Independent Claim 161 words
A method of fabricating a monolithic PIN diode in a wafer of semiconductor material having a substrate that forms a first a majority charge region and an overlying layer that forms an I region, the method comprising the steps of: removing the overlying layer from the substrate around each of two predefined areas whereby the remaining overlying layer forms first and second I region mesas on the substrate, each mesa having an upper surface; forming a second majority charge region in the upper portion of the second mesa, the second majority charge region being of opposite polarity to the first majority charge region, and separated from the first majority charge region by the intervening I region of the second mesa; applying insulation to the exposed surfaces of the mesas and the substrate, the insulation having a first opening located between the mesas for access to the substrate, and a second opening for access to the upper surface of the second mesa;
Claim 3
Dependent Claim 64 words
forming contact layers on the first and second mesas, the contact layer on the second mesa making electrical contact with the second majority charge region; and providing a conductive path between the first opening and the contact atop the first mesa, the conductive path connecting the contact to the substrate, but being isolated by the insulation from the I region in the first mesa.
Claim 4
Dependent Claim 64 words
forming contact layers on the first and second mesas, the contact layer on the second mesa making electrical contact with the second majority charge region; and providing a conductive path between the first opening and the contact atop the first mesa, the conductive path connecting the contact to the substrate, but being isolated by the insulation from the I region in the first mesa.

References Cited (Backward Citations)

US3436279A Cited
US3659156A Cited
US3746587A Cited
US4051507A Cited
JPS53139990A Cited
US4297783A Cited
EP0064918A2 Cited
US4570332A Cited
JPS59181055A Cited
US4571559A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-04-19 1991-10-19 1992-04-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-04-19 1995-10-19 1996-04-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-04-19 1999-10-19 2000-04-19 $7700.00 Window Closed / Lapsed

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