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US4739388A
Expired / Lapsed
US
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Integrated circuit structure for a quality check of a semiconductor substrate wafer
Assignee: Siemens AG
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Filing: 1986-08-27
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Granted: 1988-04-19
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Expires: 2006-08-27
Abstract
Abstract An integrated circuit structure to be built on a semiconductor substrate wafer for the purpose of undertaking a quality check of the wafer has a plurality of field effect transistors laterally disposed in the same close adjacency as transistors which are to be manufactured on a chip using the wafer material. Each field effect transistor has its own well structure, its own source structure, and its own drain structure. The individual field effect transistors have pads allocated thereto at an edge of the structure. Each transistor source/drain structure is connected to the pads by a conductor, the totality of these conductors having width and/or length dimensions so that each run has approximately the same resistance. Only one common gate conductor for all of the transistors is provided.
Inventors
- 👤 Gerhard Packeiser
- 👤 Helmut Schink
- 👤 Gerard M. Martin
- 👤 Jose Maluenda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:26
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/20; H10P74/207; G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; H10P74/23; H10P74/27; H10P74/277; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
183 words
A structure for use in making a quality check of a substrate wafer consisting of semiconductor material produced from a larger semiconductor crystal, the substrate wafer to be employed for manufacturing chips having integrated circuits thereon, said structure comprising: a plurality of field effect transistor structures disposed directly on a surface of said substrate wafer with the same density as the density of the functional components in said integrated circuit to be manufactured on said substrate wafer, said field effect transistors being disposed side by side on said substrate wafer; each field effect transistor structure having an individual well structure within said substrate, and individual source structure, and an individual drain structure; a plurality of terminal pads disposed at an edge region of said structure; a plurality of conductors on said substrate respectively connecting a source and drain structure of a field effect transistor to one of said terminal pads, each of said conductors having dimensions such that the impedance of each conductor is substantially identical; and a single common gate conductor for common connection to all of said field effect transistor structures.
Claim 2
Dependent Claim
183 words
A structure for use in making a quality check of a substrate wafer consisting of semiconductor material produced from a larger semiconductor crystal, the substrate wafer to be employed for manufacturing chips having integrated circuits thereon, said structure comprising: a plurality of field effect transistor structures disposed directly on a surface of said substrate wafer with the same density as the density of the functional components in said integrated circuit to be manufactured on said substrate wafer, said field effect transistors being disposed side by side on said substrate wafer; each field effect transistor structure having an individual well structure within said substrate, and individual source structure, and an individual drain structure; a plurality of terminal pads disposed at an edge region of said structure; a plurality of conductors on said substrate respectively connecting a source and drain structure of a field effect transistor to one of said terminal pads, each of said conductors having dimensions such that the impedance of each conductor is substantially identical; and a single common gate conductor for common connection to all of said field effect transistor structures.
Claim 3
Dependent Claim
29 words
A structure as claimed in claim 1, wherein said gate conductor is connected to each field effect transistor structure at two opposite sides of said field effect transistor structure.
Claim 4
Dependent Claim
24 words
A structure as claimed in claim 1, wherein said gate conductor is connected to each field effect transistor structure via a Schottky gate contact.
Claim 5
Dependent Claim
29 words
A structure as claimed in claim 1, wherein at least a portion of said conductors are dimensioned for providing said identical resistance by a meandering path of selected length.
Claim 6
Dependent Claim
29 words
A structure as claimed in claim 1, wherein at least a portion of said conductors are dimensioned to obtain said identical resistance by an angled section of selected length.
Claim 7
Dependent Claim
22 words
A structure as claimed in claim 1, wherein said conductors are disposed on said substrate such that no conductor crosses another conductor.
Claim 8
Dependent Claim
26 words
A structure as claimed in claim 1, wherein said individual well structure for each field effect transistor structure is a doped region of said substrate wafer.
Claim 9
Dependent Claim
28 words
A structure as claimed in claim 1, wherein the semiconductor material of said wafer surrounding each individual well structure in said field effect transistor structures is electrically insulating.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-19 | 1991-10-19 | 1992-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-19 | 1995-10-19 | 1996-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-19 | 1999-10-19 | 2000-04-19 | $7700.00 | Window Closed / Lapsed |