Method for producing a protective arrangement for a field-effect transistor

Claim 1

Process for the production of a protective arrangement for a field effect transistor with an insulated gate electrode using an integrated, in-diffused protective diode whose breakdown voltage is less than that of the gate insulating layer of the transistor, Wherein first impurities producing the first conduction type are implanted in the surface of a substrate of the first conduction type in the surface area provided for the protective diode, wherein second impurities producing the first conduction type are then implanted in the surface of the substrate with the exception of the area provided for the field-ffect transistor, and wherein, finally, the source zone and the drain zone and a third zone of the second conduction type forming the protective diode are diffused into the substrate.

Claim 4

A method of producing a protective arrangement for a field effect transistor having an insulated gate electrode and employing an integrated, in-diffused protective diode whose breakdown voltage is less than that of the gate insulating layer and which has one of its electrodes connected with said gate electrode, comprising the steps of: implanting first impurities which produce the first conductivity type in a first region of the surface of a substrate of the first conductivity type; thereafter, implanting second impurities producing said first conductivity type in the surface of the substrate except for the portion of the substrate surface intended for the channel region of the field effect transistor; and thereafter, simlutaneously diffusing the source zone and the drain zone of the transistor and a third zone for the protective diode, which are all of the second conductivity type, into the surface of said substrate with said third zone being formed at least partially within said first region so as to form a pn-junction with the substrate which at least partially, extends to said substrate surface within said first region; and wherein the implantation quantities are selected such that the desired break-down voltage of the protective diode is realized in said first region due to both of the implantations, while the field inversion voltage is increased in the remaining regions of the substrate surface due to the second implantation.

Claim 5

A method of producing a protective arrangement for a field effect transistor having an insulated gate electrode and employing an integrated, in-diffused protective diode whose breakdown voltage is less than that of the gate insulating layer and which has one of its electrodes connected with said gate electrode, comprising the steps of: implanting first impurities which produce the first conductivity type in a first region of the surface of a substrate of the first conductivity type; thereafter, implanting second impurities producing said first conductivity type in the surface of the substrate except for the portion of the substrate surface intended for the channel region of the field effect transistor; and thereafter, simlutaneously diffusing the source zone and the drain zone of the transistor and a third zone for the protective diode, which are all of the second conductivity type, into the surface of said substrate with said third zone being formed at least partially within said first region so as to form a pn-junction with the substrate which at least partially, extends to said substrate surface within said first region; and wherein the implantation quantities are selected such that the desired break-down voltage of the protective diode is realized in said first region due to both of the implantations, while the field inversion voltage is increased in the remaining regions of the substrate surface due to the second implantation.