US4745079A
Expired / Lapsed
US
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Method for fabricating MOS transistors having gates with different work functions
Assignee: Motorola Solutions Inc
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Filing: 1987-03-30
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Granted: 1988-05-17
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Expires: 2007-03-30
Abstract
Abstract A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.
Inventors
- 👤 James R. Pfiester
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322; H10D64/60; H10D64/66; H10D64/671; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
156 words
A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a semiconductor substrate; forming a layer of gate dielectric material on the semiconductor substrate; forming a layer of semiconductor material on the gate dielectric material layer; providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed; introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer; diffusing the impurity of the first conductivity type a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking material pattern, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type; and providing an impurity of a second conductivity type into the central portion.
Claim 2
Independent Claim
156 words
A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a semiconductor substrate; forming a layer of gate dielectric material on the semiconductor substrate; forming a layer of semiconductor material on the gate dielectric material layer; providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed; introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer; diffusing the impurity of the first conductivity type a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking material pattern, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type; and providing an impurity of a second conductivity type into the central portion.
Claim 3
Dependent Claim
30 words
The process of claim 1 wherein a thin layer of dielectric material is provided on top of the layer of semiconductor material before the formation of the masking material pattern.
Claim 4
Dependent Claim
50 words
The process of claim 1 wherein a thin layer of dielectric material is provided over the gate after the selected areas of the semiconductor material are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.
Claim 5
Dependent Claim
47 words
The process of claim 1 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.
Claim 6
Dependent Claim
66 words
The process of claim 1 wherein after the diffusion of the impurity of the first conductivity type a selected distance laterally into the semiconductor material layer, the selected areas of the semiconductor material are removed to leave a gate of semiconductor material having end portions and a central portion between the end portions, the end portions being doped with the impurity of a first conductivity type.
Claim 7
Dependent Claim
59 words
The process of claim 5 wherein after the selected areas of the semiconductor material layer are removed, an impurity of a second conductivity type is introduced into the central portion of the gate and the semiconductor substrate using the gate as mask to simultaneously form a doped central portion and doped source/drain regions respectively, of a second conductivity type.
Claim 8
Dependent Claim
23 words
The process of claim 5 wherein the pattern of masking material is removed after the selected areas of the semiconductor material are removed.
Claim 9
Independent Claim
209 words
A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a semiconductor substrate lightly doped with an impurity; forming a layer of gate dielectric material on the semiconductor substrate; forming a layer of semiconductor material on the gate dielectric material layer; providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed; introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer; diffusing the impurity of the first conductivity type in the selected areas of the semiconductor material layer a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking layer, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type; removing the selected areas of the semiconductor material to leave a gate of semiconductor material having end portions and the central portion between the end portions, the end portions being lightly doped with the impurity of the first conductivity type; and providing an impurity of a second conductivity type in the central portion.
Claim 10
Independent Claim
209 words
A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a semiconductor substrate lightly doped with an impurity; forming a layer of gate dielectric material on the semiconductor substrate; forming a layer of semiconductor material on the gate dielectric material layer; providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed; introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer; diffusing the impurity of the first conductivity type in the selected areas of the semiconductor material layer a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking layer, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type; removing the selected areas of the semiconductor material to leave a gate of semiconductor material having end portions and the central portion between the end portions, the end portions being lightly doped with the impurity of the first conductivity type; and providing an impurity of a second conductivity type in the central portion.
Claim 11
Dependent Claim
30 words
The process of claim 8 wherein a thin layer of silicon dioxide is provided on top of the layer of semiconductor material before the formation of the masking material pattern.
Claim 12
Dependent Claim
50 words
The process of claim 8 wherein a thin layer of silicon dioxide is provided over the gate after the selected areas of the semiconductor material are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.
Claim 13
Dependent Claim
47 words
The process of claim 8 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.
Claim 14
Dependent Claim
61 words
The method of claim 8 wherein after the selected areas of the semiconductor material layer are removed, an impurity of a second conductivity type is introduced into the central portion of the gate and the semiconductor substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.
Claim 15
Dependent Claim
24 words
The method of claim 8 wherein after the selected areas of the semiconductor material layer are removed, the pattern of masking material is removed.
Claim 16
Dependent Claim
206 words
A process for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a monocrystalline silicon substrate lightly doped with an impurity of a first conductivity type; forming a layer of gate silicon oxide on the silicon substrate; forming a layer of undoped polycrystalline silicon on the gate silicon oxide layer; providing a pattern of masking material on the layer of polycrystalline silicon, through which selected areas of the layer of polycrystalline silicon are exposed; introducing an impurity of the first conductivity type into the selected areas of the polycrystalline silicon layer; diffusing the impurity of the first conductivity type in the selected areas of the polycrystalline silicon layer a selected distance into the polycrystalline silicon layer laterally under the masking material pattern; removing the selected areas of the polycrystalline silicon to leave a polycrystalline silicon gate having end portions and a central portion therebetween, the end portions being lightly doped with the impurity of a first conductivity type; and introducing an impurity of a second conductivity type into the central portion of the gate and the silicon substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.
Claim 17
Dependent Claim
206 words
A process for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of: providing a monocrystalline silicon substrate lightly doped with an impurity of a first conductivity type; forming a layer of gate silicon oxide on the silicon substrate; forming a layer of undoped polycrystalline silicon on the gate silicon oxide layer; providing a pattern of masking material on the layer of polycrystalline silicon, through which selected areas of the layer of polycrystalline silicon are exposed; introducing an impurity of the first conductivity type into the selected areas of the polycrystalline silicon layer; diffusing the impurity of the first conductivity type in the selected areas of the polycrystalline silicon layer a selected distance into the polycrystalline silicon layer laterally under the masking material pattern; removing the selected areas of the polycrystalline silicon to leave a polycrystalline silicon gate having end portions and a central portion therebetween, the end portions being lightly doped with the impurity of a first conductivity type; and introducing an impurity of a second conductivity type into the central portion of the gate and the silicon substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.
Claim 18
Dependent Claim
27 words
The process of claim 14 wherein the polycrystalline silicon layer is doped with an impurity after it is formed and before the masking material pattern is provided.
Claim 19
Dependent Claim
29 words
The process of claim 14 wherein a thin layer of silicon dioxide is provided on top of the polycrystalline silicon layer before the formation of the masking material pattern.
Claim 20
Dependent Claim
30 words
The process of claim 14 wherein the masking material pattern is selected from the group consisting of silicon oxide, silicon nitride and a combination of silicon oxide and silicon nitride.
Claim 21
Dependent Claim
51 words
The process of claim 14 wherein a thin layer of silicon dioxide is provided over the gate after the selected areas of the polycrystalline silicon layer are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.
Claim 22
Dependent Claim
47 words
The process of claim 14 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.
Claim 23
Dependent Claim
31 words
The process of claim 14 wherein the strap of conductive material is selected from the group consisting of doped semiconductor material, a metal, a refractory metal silicide or a combination thereof.
Claim 24
Dependent Claim
23 words
The process of claim 14 wherein the pattern of masking material is removed after the removal of the selected area of polycrystalline silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-17 | 1991-11-16 | 1992-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-17 | 1995-11-16 | 1996-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-17 | 1999-11-16 | 2000-05-17 | $7700.00 | Window Closed / Lapsed |