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Patent US4746624A successfully refreshed from Google Patents.
US4746624A
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US
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Method for making an LDD MOSFET with a shifted buried layer and a blocking region
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1986-10-31
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Granted: 1988-05-24
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Expires: 2006-10-31
Abstract
Abstract A MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain. The buried region, which is doped to a level intermediate between that of the tip region and the drain, causes the channel current to deflect downwardly from the field oxide, through the lightly doped tip region, and into the buried region. The gradual electric field gradient produced by the structure and the deflection of the channel current away from the thin oxide greatly reduces the device's sensitivity to the hot electron effect. The method of the invention includes forming the lightly doped tip region, forming a first oxide spacer, forming the buried region, widening the oxide spacer, and finally forming the drain region.
Inventors
- 👤 Kit M. Cham
- 👤 Paul V. Voorde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:49
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/021; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
137 words
A method for producing an n-channel MOSFET device in a semiconductor substrate comprising the steps of: forming a gate structure over a region of said substrate; forming a lightly doped n-type tip region in said substrate in substantial alignment with said gate structure; forming first spacer means having a first width against said gate structure; implanting an n-type buried region; forming second spacer means having a second width greater than said first width against said gate structure; and forming a heavily doped n-type source region and a heavily doped n-type drain region wherein said buried region has a doping level intermediate to that of said tip region and said drain region; and forming a blocking region between said tip region and said drain region after forming said first spacer means but before forming said second spacer means.
Claim 2
Independent Claim
137 words
A method for producing an n-channel MOSFET device in a semiconductor substrate comprising the steps of: forming a gate structure over a region of said substrate; forming a lightly doped n-type tip region in said substrate in substantial alignment with said gate structure; forming first spacer means having a first width against said gate structure; implanting an n-type buried region; forming second spacer means having a second width greater than said first width against said gate structure; and forming a heavily doped n-type source region and a heavily doped n-type drain region wherein said buried region has a doping level intermediate to that of said tip region and said drain region; and forming a blocking region between said tip region and said drain region after forming said first spacer means but before forming said second spacer means.
Claim 3
Dependent Claim
29 words
A method for producing a MOSFET device as recited in claim 1 wherein said blocking region is an n-type region which is more lightly doped than said tip region.
Claim 4
Dependent Claim
19 words
A method for producing a MOSFET device as recited in claim 1 wherein said blocking region is substantially intrinsic.
Claim 5
Dependent Claim
22 words
A method for producing a MOSFET device as recited in claim 1 wherein said blocking region is a lightly doped p-type region.
Claim 6
Independent Claim
102 words
A method for producing a MOSFET device comprising the steps of: forming a gate structure over a region of said substrate; forming a tip region in said substrate in substantial alignment with said gate structure; forming first spacer means having a first width against said gate structure; implanting a buried region; forming second spacer means having a second width greater than said first width against said gate structure; forming a source region and a drain region; and forming a blocking region between said tip region and said drain region after forming said first spacer means but before forming said second spacer means.
Claim 7
Independent Claim
102 words
A method for producing a MOSFET device comprising the steps of: forming a gate structure over a region of said substrate; forming a tip region in said substrate in substantial alignment with said gate structure; forming first spacer means having a first width against said gate structure; implanting a buried region; forming second spacer means having a second width greater than said first width against said gate structure; forming a source region and a drain region; and forming a blocking region between said tip region and said drain region after forming said first spacer means but before forming said second spacer means.
Claim 8
Dependent Claim
33 words
A method for producing a MOSFET device as recited in claim 5 wherein said step of producing said first spacer means includes forming first oxide spacers along opposing sides of said gate structure.
Claim 9
Dependent Claim
31 words
A method for producing a MOSFET device as recited in claim 6 wherein said step of producing said second spacer means includes forming second oxide spacers on said first oxide spacers.
Claim 10
Independent Claim
148 words
A method for producing a MOSFET device in association with a p-type semiconductor substrate comprising the steps of: forming a gate structure including a thin oxide layer located over an n-type channel region in said substrate, and a conductive gate located over said thin oxide layer; forming self-aligned, lightly doped, n-type tip regions in said substrate on opposing sides of said channel region; forming oxide spacers along opposing sides of said gate structure; implanting self-aligned, intermediately doped, n-type buried regions in said substrate beneath said tip regions; widening said oxide spacers; forming self-aligned, heavily doped, n-type source and drain regions in said substrate such that said tip regions and said buried regions are located between said source and said drain regions; and forming blocking regions between said tip regions and said source region and said drain region after forming said oxide spacers but before widening said oxide spacers.
Claim 11
Independent Claim
148 words
A method for producing a MOSFET device in association with a p-type semiconductor substrate comprising the steps of: forming a gate structure including a thin oxide layer located over an n-type channel region in said substrate, and a conductive gate located over said thin oxide layer; forming self-aligned, lightly doped, n-type tip regions in said substrate on opposing sides of said channel region; forming oxide spacers along opposing sides of said gate structure; implanting self-aligned, intermediately doped, n-type buried regions in said substrate beneath said tip regions; widening said oxide spacers; forming self-aligned, heavily doped, n-type source and drain regions in said substrate such that said tip regions and said buried regions are located between said source and said drain regions; and forming blocking regions between said tip regions and said source region and said drain region after forming said oxide spacers but before widening said oxide spacers.
Claim 12
Dependent Claim
52 words
A method for producing a MOSFET device as recited in claim 8 wherein said tip regions, said buried regions, said source regions, and said drain regions are formed by the implantation ions which form n-type materials, and wherein said blocking region is formed by the implantation of ion which form p-type materials.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-24 | 1991-11-23 | 1992-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-24 | 1995-11-23 | 1996-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-24 | 1999-11-23 | 2000-05-24 | $7700.00 | Window Closed / Lapsed |