IIR digital filter

Claim 2

A digital filter of the infinite impulse response type for filtering a digital signal sampled at a predetermined sampling frequency and having an original system function including a first order term at least in its denominator, said digital filter converting said original system function to a new system function which is equivalent to said original system function and which corresponds to the result of multiplying each of said denominator and a numerator of said original system function by the same polynomial expression such that said first order term is eliminated in a denominator of said new system function; said digital filter comprising: first delay circuit means having an input and an output for delaying an input signal received at said input and including said digital signal for one period of said sampling frequency and producing a delayed output signal at said output; feedback circuit means connected between the output and input of said first delay circuit means and including multiplying circuit means for multiplying said delayed output signal by a coefficient determined by the denominator of said new system function and second delay circuit means for delaying the multiplied signal for said one period to provide a feedback signal; adder means for adding said input digital signal and said feedback signal of said feedback circuit means, an output signal of said adder means being supplied to said first delay circuit means as said input signal thereto; filter means of the finite impulse response type corresponding to said polynomial expression; and means for connecting said filter means to the output of said first delay circuit means.

Claim 3

A digital filter of the infinite impulse response type for filtering a digital signal sampled at a predetermined sampling frequency and having an original system function including a first order term at least in its denominator and a second order polynomial expression in said denominator, said second order polynomial expression being expressed as follows, ##EQU4## said digital filter converting said original system function to a new system function which is equivalent to said original system function and which corresponds to the result of multiplying each of said denominator and a numerator of said original system function by the same polynomial expression which is (1-b 2 z -2 )+b 1 z -1 , such that said first order term is eliminated in a denominator of said new system function; said digital filter comprising: first delay circuit means having an input and an output for delaying an input signal received at said input and including said digital signal for one period of said sampling frequency and producing a delayed output signal at said output; first feedback circuit means connected between the output and input of said first delay circuit means and including multiplying circuit means for multiplying said delayed output signal by a coefficient determined by the denominator of said new system function and second delay circuit means for delaying the multiplied signal for said one period to provide a feedback signal; first adder means for adding said input digital signal and said feedback signal of said first feedback circuit means, an output signal of said first adder means being supplied to said first delay circuit means as said input signal thereto; filter means of the finite impulse response type corresponding to said polynomial expression; means for connecting said filter means to the output of said first delay circuit means; second adder means receiving said input digital signal and third delay circuit means for delaying a received signal for said one period connected in series to supply said input digital signal to said first adder means; and second feedback circuit means connected between the output of said first delay circuit means and an input of said second adder means, said second feedback circuit means including second multiplying circuit means for multiplying said delayed output signal by a second coefficient determined by a denominator of said new system function and fourth and fifth delay circuit means each of which delays the multiplied signal for said one period.

Claim 4

A digital filter of the infinite impulse response type for filtering a digital signal sampled at a predetermined sampling frequency and having an original system function including a first order term at least in its denominator and a second order polynomial expression in said denominator, said second order polynomial expression being expressed as follows, ##EQU4## said digital filter converting said original system function to a new system function which is equivalent to said original system function and which corresponds to the result of multiplying each of said denominator and a numerator of said original system function by the same polynomial expression which is (1-b 2 z -2 )+b 1 z -1 , such that said first order term is eliminated in a denominator of said new system function; said digital filter comprising: first delay circuit means having an input and an output for delaying an input signal received at said input and including said digital signal for one period of said sampling frequency and producing a delayed output signal at said output; first feedback circuit means connected between the output and input of said first delay circuit means and including multiplying circuit means for multiplying said delayed output signal by a coefficient determined by the denominator of said new system function and second delay circuit means for delaying the multiplied signal for said one period to provide a feedback signal; first adder means for adding said input digital signal and said feedback signal of said first feedback circuit means, an output signal of said first adder means being supplied to said first delay circuit means as said input signal thereto; filter means of the finite impulse response type corresponding to said polynomial expression; means for connecting said filter means to the output of said first delay circuit means; second adder means receiving said input digital signal and third delay circuit means for delaying a received signal for said one period connected in series to supply said input digital signal to said first adder means; and second feedback circuit means connected between the output of said first delay circuit means and an input of said second adder means, said second feedback circuit means including second multiplying circuit means for multiplying said delayed output signal by a second coefficient determined by a denominator of said new system function and fourth and fifth delay circuit means each of which delays the multiplied signal for said one period.

Claim 5

A digital filter of the infinite impulse response type for filtering a digital signal sampled at a predetermined sampling frequency and having an original system function including a first order term at least in its denominator and a second order polynomial expression in said denominator, said second order polynomial expression being expressed as follows, ##EQU5## said digital filter converting said original system function to a new system function which is equivalent to said original system function and which corresponds to the result of multiplying each of said denominator and a numerator of said original system function by the same polynomial expression which is (1-b 2 z -2 )+b 1 z -1 , so that said first order term is eliminated in a denominator of said new system function; said digital filter comprising: first delay circuit means having an input and an output for delaying an input signal received at said input and including said digital signal for one period of said sampling frequency and producing a delayed output signal at said output; first feedback circuit means connected between the output and input of said first delay circuit means and including multiplying circuit means for multiplying said delayed output signal by a coefficient determined by the denominator of said new system function and second delay circuit means for delaying the multiplied signal for said one period to provide a feedback signal; adder means for adding said input digital signal and said feedback signal of said first feedback circuit means, an output signal of said adder means being supplied to said first delay circuit means as said input signal thereto; filter means of the finite impulse response type corresponding to said polynomial expression; means for connecting said filter means to the output of said first delay circuit means; third delay circuit means connected to the input of said first delay circuit means for delaying said input digital signal for said one period to provide a second delayed output signal at an output; and second feedback circuit means connected between the output of said third delay circuit means and said adder means, said second feedback circuit means including second multiplying circuit means for multiplying said second delayed output signal by a second coefficient determined by the denominator of said new system function and fourth and fifth delay circuit means each of which successively delays the multiplied signal for said one period.

Claim 6

A digital filter of the infinite impulse response type for filtering a digital signal sampled at a predetermined sampling frequency and having an original system function including a first order term at least in its denominator and a second order polynomial expression in said denominator, said second order polynomial expression being expressed as follows, ##EQU5## said digital filter converting said original system function to a new system function which is equivalent to said original system function and which corresponds to the result of multiplying each of said denominator and a numerator of said original system function by the same polynomial expression which is (1-b 2 z -2 )+b 1 z -1 , so that said first order term is eliminated in a denominator of said new system function; said digital filter comprising: first delay circuit means having an input and an output for delaying an input signal received at said input and including said digital signal for one period of said sampling frequency and producing a delayed output signal at said output; first feedback circuit means connected between the output and input of said first delay circuit means and including multiplying circuit means for multiplying said delayed output signal by a coefficient determined by the denominator of said new system function and second delay circuit means for delaying the multiplied signal for said one period to provide a feedback signal; adder means for adding said input digital signal and said feedback signal of said first feedback circuit means, an output signal of said adder means being supplied to said first delay circuit means as said input signal thereto; filter means of the finite impulse response type corresponding to said polynomial expression; means for connecting said filter means to the output of said first delay circuit means; third delay circuit means connected to the input of said first delay circuit means for delaying said input digital signal for said one period to provide a second delayed output signal at an output; and second feedback circuit means connected between the output of said third delay circuit means and said adder means, said second feedback circuit means including second multiplying circuit means for multiplying said second delayed output signal by a second coefficient determined by the denominator of said new system function and fourth and fifth delay circuit means each of which successively delays the multiplied signal for said one period.