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US4761756A
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Signed multiplier with three port adder and automatic adjustment for signed operands
Assignee: Fujitsu IT Holdings Inc
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Filing: 1986-07-11
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Granted: 1988-08-02
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Expires: 2006-07-11
Abstract
Abstract Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs of the multiplier and multiplicand. While the multiplication is in progress, the signs of the multiplier and multiplicand are checked. For multiplications where either one of the operands (multiplier or multiplicand) is negative, the preliminary product is modified by one or two correction factors. The correction factors are multiplies of the 2's complements of the operands. The correction factor or factors are added to the preliminary product to form the final product.
Inventors
- 👤 Hsiao-Peng S. Lee
- 👤 John C. Oneto
- 👤 Stephen J. Rawlinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:44
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
505 words
An apparatus for multiplying a first operand having a sign by a second operand having a sign in 2's complement form to provide a final product, comprising: a first register for storing the first operand; means, coupled to the first register, for generating a complement of the first operand; a second register for storing the second operand; means, coupled to the second register, for generating a complement of the second operand; means, coupled to the first register and the second register to receive the first operand and an increment of the second operand, for multiplying the first operand by the increment of the second operand to generate a partial sum output and a partial carry output; third register means, coupled to the means for multiplying, for storing the partial sum output and the partial carry output; a result register; three port adder means, having a first port, a second port and a third port, for adding data received at the first, second and third ports to generate a resulting sum and supplying the resulting sum to the result register, the first port, second port and third port connected to receive in any given machine cycle up to three of the following data, the partial sum output from the third register, the partial carry output of the third register, the first operand, the complement of the first operand, the second operand, the complement of the second operand, the contents of the result register or zero; control means, coupled to the means for multiplying and the three port adder means, for controlling the means for multiplying and the three port adder means to successively generate partial sum and carry outputs and to add the partial sum and carry outputs to the contents of the result register to generate a partial product until a final partial product is generated; and adjustment means, responsive to the sign of the first operand and of the second operand for generating an adjustment, the adjustment being determined by a first condition in which the first operand is negative and the second operand is positive, a second condition in which the first operand is positive and the second operand is negative, and a third condition in which both the first and second operands are negative, including means, responsive to the first condition, for controlling the adder means to add the complement of the second operand to contents of high order bits of a final partial product in the result register, means, responsive to the second condition, for controlling the adder means to add the complement of the first operand to the contents of the result register before generation of a partial product, and means, responsive to the third condition, for controlling the adder means to add a multiple of the complement of the first operand to the contents of the result register before generation of a partial product and to add a multiple of the complement of the second operand to high order bits of the final partial product in the result register.
Claim 2
Independent Claim
505 words
An apparatus for multiplying a first operand having a sign by a second operand having a sign in 2's complement form to provide a final product, comprising: a first register for storing the first operand; means, coupled to the first register, for generating a complement of the first operand; a second register for storing the second operand; means, coupled to the second register, for generating a complement of the second operand; means, coupled to the first register and the second register to receive the first operand and an increment of the second operand, for multiplying the first operand by the increment of the second operand to generate a partial sum output and a partial carry output; third register means, coupled to the means for multiplying, for storing the partial sum output and the partial carry output; a result register; three port adder means, having a first port, a second port and a third port, for adding data received at the first, second and third ports to generate a resulting sum and supplying the resulting sum to the result register, the first port, second port and third port connected to receive in any given machine cycle up to three of the following data, the partial sum output from the third register, the partial carry output of the third register, the first operand, the complement of the first operand, the second operand, the complement of the second operand, the contents of the result register or zero; control means, coupled to the means for multiplying and the three port adder means, for controlling the means for multiplying and the three port adder means to successively generate partial sum and carry outputs and to add the partial sum and carry outputs to the contents of the result register to generate a partial product until a final partial product is generated; and adjustment means, responsive to the sign of the first operand and of the second operand for generating an adjustment, the adjustment being determined by a first condition in which the first operand is negative and the second operand is positive, a second condition in which the first operand is positive and the second operand is negative, and a third condition in which both the first and second operands are negative, including means, responsive to the first condition, for controlling the adder means to add the complement of the second operand to contents of high order bits of a final partial product in the result register, means, responsive to the second condition, for controlling the adder means to add the complement of the first operand to the contents of the result register before generation of a partial product, and means, responsive to the third condition, for controlling the adder means to add a multiple of the complement of the first operand to the contents of the result register before generation of a partial product and to add a multiple of the complement of the second operand to high order bits of the final partial product in the result register.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1, wherein the adjustment means generates the adjustment in a single cycle.
Claim 4
Dependent Claim
23 words
The apparatus of claim 1, wherein the adjustment means generates the adjustment in a single cycle after generation of the final partial product.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-02 | 1992-02-01 | 1992-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-02 | 1996-02-01 | 1996-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-02 | 2000-02-01 | 2000-08-02 | $7700.00 | Window Closed / Lapsed |