Patent US4763318A successfully refreshed from Google Patents.
US4763318A
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Transmission and reception of synchronous data and timing signals using a steady bit stream
Assignee: Datos Corp
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Filing: 1986-05-02
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Granted: 1988-08-09
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Expires: 2006-05-02
Abstract
Abstract In an telecommunications switching system, user clock data is "massively sampled" at the source node with reference to a global clock signal, and reconstructed with no more than allowable error at the destination. Massive sampling and reconstruction of the clock signal allows users of the transmission system to send data at arbitrary data rates and to perform their own clock synchronization at a different protocol level from the hardware switching system. Direct use of the global system clock rate of approximately 192 kilobits per second (kbps) is provided for by synchronizing the user data with the global clock signal.
Inventors
- 👤 James E. Westbrook
- 👤 Adolfo B. Suarez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:56
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/068
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
104 words
In a distributed data-over-voice communication system with a global system clock, said global system clock having a data rate substantially greater than a transmission rate of asynchronous data signals in said system, a method of routing said data signals from a source device to a destination device, comprising the steps of sampling said asynchronous data signals with reference to said global system clock to generate sampling data signals; routing said sampling data signals from said source device to said destination device; and decoding said sampling data signals with reference to said global system clock to reconstruct said asynchronous data signals by said destination device.
Claim 2
Dependent Claim
104 words
In a distributed data-over-voice communication system with a global system clock, said global system clock having a data rate substantially greater than a transmission rate of asynchronous data signals in said system, a method of routing said data signals from a source device to a destination device, comprising the steps of sampling said asynchronous data signals with reference to said global system clock to generate sampling data signals; routing said sampling data signals from said source device to said destination device; and decoding said sampling data signals with reference to said global system clock to reconstruct said asynchronous data signals by said destination device.
Claim 3
Dependent Claim
158 words
In a distributed switching system with a global system clock, a method of routing synchronous clock signals, having a plurality of timing periods, and data signals, having a plurality of data bits each corresponding to a timing period of said clock signals, from a source device to a destination device, comprising the steps of: (a) sampling said synchronous clock signals with reference to said global system clock to generate sampling clock signals, each timing period of which comprises a plurality of global system clock pulses; (b) for each timing period of said sampling clock signals, altering a later global system clock pulse after the clock transition to equal the corresponding data bit of said data signals; (c) routing said altered sampling clock signals from said source device to said destination device; and (d) decoding said sampling clock signals with reference to said global system clock to reconstruct said synchronous clock signals and data signals by said destination device.
Claim 4
Dependent Claim
158 words
In a distributed switching system with a global system clock, a method of routing synchronous clock signals, having a plurality of timing periods, and data signals, having a plurality of data bits each corresponding to a timing period of said clock signals, from a source device to a destination device, comprising the steps of: (a) sampling said synchronous clock signals with reference to said global system clock to generate sampling clock signals, each timing period of which comprises a plurality of global system clock pulses; (b) for each timing period of said sampling clock signals, altering a later global system clock pulse after the clock transition to equal the corresponding data bit of said data signals; (c) routing said altered sampling clock signals from said source device to said destination device; and (d) decoding said sampling clock signals with reference to said global system clock to reconstruct said synchronous clock signals and data signals by said destination device.
Claim 5
Dependent Claim
106 words
In a distributed data-over-voice communication system with a global system clock, said global system clock having a data rate substantially greater than a transmission rate of asynchronous data signals in said system, a device for routing said data signals from a source device to a destination device, comprising means for sampling said asynchronous data signals with reference to said global system clock to generate sampling data signals; means for routing said sampling data signals from said source device to said destination device; and means for decoding said sampling data signals with reference to said global system to reconstruct said asynchronous data signals by said destination device.
Claim 6
Dependent Claim
106 words
In a distributed data-over-voice communication system with a global system clock, said global system clock having a data rate substantially greater than a transmission rate of asynchronous data signals in said system, a device for routing said data signals from a source device to a destination device, comprising means for sampling said asynchronous data signals with reference to said global system clock to generate sampling data signals; means for routing said sampling data signals from said source device to said destination device; and means for decoding said sampling data signals with reference to said global system to reconstruct said asynchronous data signals by said destination device.
Claim 7
Dependent Claim
163 words
In a distributed switching system with a global system clock, a device for routing synchronous clock signals, having a plurality of timing periods, and data signals, having a plurality of data bits each corresponding to a timing period of said clock signals, from a source device to a destination device, comprising (a) means for sampling said synchronous clock signals with reference to said global system clock to generate sampling clock signals, each timing period of which comprises a plurality of global system clock pulses; (b) means for altering a later global system clock pulse after the clock transition to equal the corresponding data bit of said data signals, for each timing period of said sampling clock signals; (c) means for routing said altered sampling clock signals from said source device to said destination device; and (d) means for decoding said sampling clock signals with reference to said global system clock to reconstruct said synchronous clock signals and data signals by said destination device.
Claim 8
Dependent Claim
163 words
In a distributed switching system with a global system clock, a device for routing synchronous clock signals, having a plurality of timing periods, and data signals, having a plurality of data bits each corresponding to a timing period of said clock signals, from a source device to a destination device, comprising (a) means for sampling said synchronous clock signals with reference to said global system clock to generate sampling clock signals, each timing period of which comprises a plurality of global system clock pulses; (b) means for altering a later global system clock pulse after the clock transition to equal the corresponding data bit of said data signals, for each timing period of said sampling clock signals; (c) means for routing said altered sampling clock signals from said source device to said destination device; and (d) means for decoding said sampling clock signals with reference to said global system clock to reconstruct said synchronous clock signals and data signals by said destination device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-09 | 1992-02-08 | 1992-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-09 | 1996-02-08 | 1996-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-09 | 2000-02-08 | 2000-08-09 | $7700.00 | Window Closed / Lapsed |