Method for fabricating self-aligned, conformal metallization of semiconductor wafer

Claim 1

A process for fabricating an integrated circuit comprising the steps of providing a substrate; forming in sequence a first dielectric layer, a thin silicon layer, and a second dielectric layer over an upper surface of said substrate; forming at least one trench in said second dielectric leaving a remaining thin layer of said second dielectric layer overlying said thin silicon layer at the bottom of the trench so formed; etching through a portion of said remaining thin layer, said underlying thin silicon layer and said underlying first dielectric layer, thereby to form a contact hole extending to the upper surface of said substrate, a portion of said thin dielectric layer remaining over a portion of said thin silicon layer at the upper part of said contact hole; thereafter, utilizing said remaining portion of said thin dielectric layer as a mask, selectively depositing a metal into said contact hole; thereafter removing said remaining portion of said thin dielectric layer leaving said portion of said thin silicon layer exposed; and thereafter selectively depositing a second metal onto said exposed part of said thin silicon layer and the upper surface of said metal-filled contact hole, thereby to fill said trench with said second metal.