Semiconductor memory device with low-noise structure

Claim 2

A semiconductor memory device of the type having a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each of said memory cells including a capacitor having a first electrode, supplied with a predetermined potential, and a second electrode; and a field effect transistor having a source-drain path, coupled between said second electrode of said capacitor and one of said bit lines, and a gate electrode coupled to one of said word lines; wherein said first electrode of said capacitor includes a conductive layer of at least one of refractory metal and silicide of said refractory metal, and comprising an auxiliary wiring layer of a highly-conductive metal formed over said conductive layer through an insulating layer, said auxiliary wiring layer being contacted with a plurality of different portions of said conductive layer.

Claim 3

The memory device according to claim 1, wherein the gate electrode of said transistor is formed of polycrystalline silicon.

Claim 4

The memory device according to claim 1, wherein said first electrode of said capacitor is made of a single consecutive pattern over a whole memory cell array.

Claim 5

The memory device according to claim 1, wherein each of said bit lines includes a diffusion region formed in a semiconductor substrate.

Claim 6

The memory device according to claim 1, wherein said refractory metal is selected from the group consisting of molybdenum, tungsten, tantalum, niobium and titanium.

Claim 7

The memory device according to claim 1, wherein said gate electrode overlaps partially with said second electrode via an insulating layer.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction perpendicular to said first direction; a plurality of memory cells formed on said substrate; each of said memory cells including: a storage capacitor having a first electrode coupled to a predetermined potential source, a second electrode and a switch transistor having a channel, for operatively interconnecting said second electrode of said storage capacitor and one of said bit lines, and a gate electrode electrically connected to one of said word lines; the first electrode of the plurality of storage capacitors being made of a polycrystalline silicon layer; an insulating film covering said polycrystalline silicon layer and having a plurality of openings spaced apart from each other; and a plurality of highly-conductive strip layers extending in said first direction and formed on said insulating film and contacted with said polycrystalline silicon layer through said openings at a plurality of different portions of said polycrystalline silicon layer.

Claim 9

A semiconductor memory device comprising: a semiconductor substrate; a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction perpendicular to said first direction; a plurality of memory cells formed on said substrate; each of said memory cells including: a storage capacitor having a first electrode coupled to a predetermined potential source, a second electrode and a switch transistor having a channel, for operatively interconnecting said second electrode of said storage capacitor and one of said bit lines, and a gate electrode electrically connected to one of said word lines; the first electrode of the plurality of storage capacitors being made of a polycrystalline silicon layer; an insulating film covering said polycrystalline silicon layer and having a plurality of openings spaced apart from each other; and a plurality of highly-conductive strip layers extending in said first direction and formed on said insulating film and contacted with said polycrystalline silicon layer through said openings at a plurality of different portions of said polycrystalline silicon layer.

Claim 10

The memory device according to claim 7, wherein the gate electrodes of the plurality of transistors are formed of polycrystalline silicon.

Claim 11

The memory device according to claim 7, wherein each of said bit lines includes a diffusion region formed in said semiconductor substrate.

Claim 12

The memory device according to claim 7, wherein said memory cells are arranged in a plurality of rows, and said highly-conductive strip layers are disposed between rows of the memory cells.

Claim 13

The memory device according to claim 7, wherein said highly-conductive strip layers are directly connected to said predetermined potential source.